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LF412C datasheet

Thu, 17 May 2012 16:35:24 -0400

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Low Input Bias Current . . . 50 pA Typ
Low Input Noise Current
SLOS010B 鈭?MARCH 1987 鈭?REVISED AUGUST 1994
D OR P PACKAGE (TOP VIEW)
0.01 pA/飪朒z Typ
Low Supply Current . . . 4.5 mA Typ
High Input impedance . . . 1012 飦?Typ
Internally Trimmed Offset Voltage
Wide Gain Bandwidth . . . 3 MHz Typ
High Slew Rate . . . 13 V/飦璼 Typ
1OUT 1
1IN 鈭?2
VCC 鈭?4
8 VCC +
6 2IN 鈭?5 2IN +
description
This device is a low-cost, high-speed, JFET-input operational amplifier with very low input offset voltage and a specified maximum input offset voltage drift. It requires low supply current yet maintains a large gain bandwidth product and a fast slew rate. In addition, the matched high-voltage JFET input provides very low input bias and offset currents.
The LF412C can be used in applications such as high-speed integrators, digital-to-analog converters, sample-and-hold circuits, and many other circuits.
The LF412C is characterized for operation from 0飩癈 to 70飩癈.
symbol (each amplifier)
AVAILABLE OPTIONS
AT 25飩癈
The D packages are available taped and reeled. Add the suffix R to the device type (ie., LF412CDR).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC +
Supply voltage, VCC 鈭?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈭?18 V
Differential input voltage, VID
Input voltage, VI (see Note 1)
Duration of output short circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 飩?30 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 飩?15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating temperature range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0飩癈 to 70飩癈
Storage temperature range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈭?65飩癈 to 150飩癈
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage.
! "# $ %
$ ! ! & '
$ $ ( )% $ ! * $ #) # $
* ## ! %
Copyright 飪?1994, Texas Instruments Incorporated
POST OFFICE BOX 655303 飩?DALLAS, TEXAS 75265 1
POST OFFICE BOX 1443 飩?HOUSTON, TEXAS 77251鈭?443
SLOS010B 鈭?MARCH 1987 鈭?REVISED AUGUST 1994
recommended operating conditions
MIN MAX
Supply voltage, VCC +
3.5 18
Supply voltage, VCC 鈭?鈭?3.5 鈭?8
electrical characteristics over operating free-air temperature range, VCC 飩?= 飩?5 V (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
VIO Input offset voltage
VIC = 0, RS = 10 k鈩?Average temperature coefficient of input offset
飪IO voltage
VIC = 0, RS = 10 k鈩?10 20鈥?IIO Input offset current搂
VIC = 0
25 100
IIB Input bias current搂
VIC = 0
50 200
VICR Common-mode input voltage range
鈭?11.5
飩?11 to
VOM Maximum peak output voltage swing
RL = 10 k鈩?飩?12 飩?13.5
AVD Large-signal differential voltage
VO = 飩?10 V, RL = 2 k鈩?25 200
Full range
15 200
ri Input resistance
TA = 25飩癈
CMRR Common-mode rejection ratio
RS 鈮?10 k鈩?70 100
kSVR Supply-voltage rejection ratio
See Note 2
70 100
ICC Supply current
4.5 6.8
鈥?Full range is 0飩癈 to 70飩癈.
鈥?At least 90% of the devices meet this limit for 飦IO.
搂 Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse techniques
must be used that will maintain the junction temperatures as close to the ambient temperature as possible.
NOTE 2: Supply-voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously.
operating characteristics, VCC 飩?= 飩?5 V, TA = 25飩癈
PARAMETER
TEST CONDITIONS
MIN TYP MAX
VO1/VO2 Crosstalk attenuation
f = 1 kHz
SR Slew rate
B1 Unity-gain bandwidth
Vn Equivalent input noise voltage
f = 1 kHz, RS = 20 鈩?nV/鈭欻z
In Equivalent input noise current
f = 1 kHz
pA/鈭欻z
2 POST OFFICE BOX 655303 飩?DALLAS, TEXAS 75265
POST OFFICE BOX 1443 飩?HOUSTON, TEXAS 77251鈭?443
PACKAGING INFORMATION
Orderable Device Status (1) Package
Package
Drawing
Pins Package
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
LF412CD
ACTIVE
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LF412CDE4
ACTIVE
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LF412CDG4
ACTIVE
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LF412CDR
ACTIVE
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LF412CDRE4
ACTIVE
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LF412CDRG4
ACTIVE
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LF412CP
ACTIVE
Pb-Free
CU NIPDAU
N / A for Pkg Type
LF412CPE4
ACTIVE
Pb-Free
CU NIPDAU
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
TAPE AND REEL BOX INFORMATION
Package
Reel Diameter (mm)
Reel Width (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1 (mm)
W (mm)
Quadrant
LF412CDR
SITE 27
Package
Length (mm)
Width (mm)
Height (mm)
LF412CDR
SITE 27
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
0.260 (6,60)
0.240 (6,10)
0.070 (1,78) MAX
0.020 (0,51) MIN
0.325 (8,26)
0.300 (7,62)
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.015 (0,38) Gage Plane
0.010 (0,25) NOM
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92) MAX
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to
POST OFFICE BOX 655303 飩?DALLAS, TEXAS 75265
IMPORTANT NOTICE
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2SA1463 datasheet

Tue, 15 May 2012 16:27:46 -0400

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DATA SHEET
SILICON TRANSISTOR
2SA1463
HIGH SPEED SWITCHINGPNP SILICON EPITAXIAL TRANSISTOR
MINI MOLD
The 2SA1463 is designed for power amplifier and high speedswitching applications.
High speed, high voltage switching.
Low Collector Saturation Voltage.
DESCRIPTION
PACKAGE DIMENSIONS
in millimeters
Complementary to the NEC 2SC3736 NPN transistor.
Collector to Emitter VoltageEmitter to Base VoltageCollector Current (DC)Collector Current (Pulse)*Maximum Power DissipationTotal Power Dissipation
3C)VCBOVCEO
-60-45-5.0-1.0-2.0
0.42 鍦?0.06 銇?EmitterCollector
-55 to +150
at 25 掳C Ambient TemperatureMaximum TemperaturesJunction TemperatureStorage Temperature Range
* PW S 10 ms. Duty Cycle ^ 50 %** When mounted on ceramic substrate of 16 cm2 x 0.7 mm
CHARACTERISTIC
SYMBOL
TESTCONDICTIONS
Collector Cutoff Current
VCE = _45 V,RBE = 0
Emitter Cutoff Current
VEB = -4.0 V, lC = 0
DC Current Gain
hFE1***
VCE = -10 V, lC;= 鈥?0 mA
DC Current Gain
hFE2禄"
VCE = -10 V, lC = 鈥?00 mA
Collector Saturation Voltage
VCE(sat)*"
lc = 涓€500 mA, Ib = -50 mA
Base Saturation Voltage
VBE(sat)**#
Gain Bandwidth Product
VCE = -10 V, IE = 100 mA
Output Capacitance
VCB = -10 V, lE = 0,f = 1.0 MHz
Turn-on Time
lc = _500 mA "'B1 = 鈥?B2 ^ 鈥?0 mA
Storage Time
Turn-off Time
ELECTRICAL CHARACTERISTICS (T=
TEST CONDUCTIONS
CHARACTERISTIC锛?VnF = -45 V,RBE = 0
Collector Cutoff Current
VFR = -4.0 V, lc = 0
Emitter Cutoff Current
VrF = -10V, lC = -50mA
DC Current Gain
VCE=_10V, lC
DC Current Gain
VcE(sat)'
Collector Saturation Voltage
)mA, Ir = 鈥?0 mA
vBE(sat)'
锛?Saturation
VCE = _10V, lE
Gain Bandwidth Product
VCr = -10V, lE
I .O MHz
Output Caoacitance
Tur闂?on Time
lc = _500 mA
IRI = 鈥擨R2 涓庘€?0 mA
Storaae Time
Turn-nft rimp
鈥ulsed: PW^ 350 jus. Duty Cycle g 2hcc Classification
MARKING
60 to 120
100 to 200
MARKING
fin to 120
in闂╰n銉昽n
漏 NEC Corporation 1987
Document No. TC鈥?1889A(O.D.No. TC-6012A)Date Published November 1994 MPrinted in JaDan
2SA1463
TYPICAL CHARACTERISTICS (Ta = 25 掳C)
TOTAL POWER DISSIPATIONAMBIENT TEMPERATURE
SAFE OPERATING AREA(TRANSIENT THERMAL RESISTANCEMETHOD)
'C(pulse) MAX.
ic(dc) max.
COLLECTOR CURRENT 鈥?COLLECTOR TO EMITTER
鈥? -2 涓€ 5 鈥?0 鈥?0 -5CVCE-Collector to Emitter Voltage-V
2 -0.4 鈥?.6 -0.8 -1.0 -1.2 涓€ 1.4 -1.6 -Vr.f-Collector to Emitter Voltage鈥擵
涓€ 1 -2 鈥?
CO銇桳ECTOR CURRENT 鈥?COLLECTOR TO EMITTER
VCE-Collector to Emitter V
COLLECTOR CURRENTBASE TO EMITTER
DC CURRENT GAIN vs. COLLECTOR CURRENT
2SA1463
GO O<0 >
=(0 O
(/) {ft
AND CO銇桳ECTOR SATURAT锛?COL銇桬CTOR CURREI
GAIN BANDWIDTH PRODUCT vs. EMITTEFCURRENT
m 10 m 20 m 50 m 100 m 200 m 500 m 1lE-Emitter Current鈥擜
VBE(sat)
1000500
ii200銉?100
Vin 100 fio 鈥?VW-
ME TEST CIRCUIT
CD O> >
m -10 m -20 m -50 m -100 m -200 m - 500 mIC鈥擟ollector Current-A
T涓€ l.U
OUTPUT CAPACITANCEREVERSE
-2 -5 -10 鈥?0 鈥斅?VCB_Collector to Base Voltage-V
搂 20(0
HING Tl
SWITCHING TIME vs. COLLECTOR CURRENT
vCc=-io V
'Bl = -lB2PW=200 nsDuty Cycle :
-10 m -20 m -50 m -100 m -200 m -500 m -1IC涓€Collector Current-A
Dutv Cvcle^2 %
鈥斺€?0 %-qo %
tste2SA1463
REFERENCE
Document Name
Document No.
NEC semiconductor device reliability/quality control system.
TEI-1202
Quality grade on NEC semiconductor devices.
IE 1-1209
Semiconductor device mounting technology manual.
IEI-1207
Semiconductor device package manual.
IEI-1213
Guide to quality assurance for semiconductor devices.
MEM 202
Semiconductor selection guide.
MF-1134
No part of this document may be copied or reproduced in any form or by. any means without the prior writtenconsent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in thisdocument.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectualproperty rights of third parties by or arising from use of a device described herein or any other liability arisingfrom use of such device. No license, either express, implied or otherwise, is granted under any patents,copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclearreactor control systems and life support systems. If customers intend to use NEC devices for above applicationsor they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contactour sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrimesystems, etc.
M4 92.6

2N5946 pdf

Tue, 15 May 2012 08:23:18 -0400

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鈥cpmrdouct,seni,鈥?I C D
MontoomeryvWePAt8936-IOI3 2N5946
RF & MICROWAVE TRANSISTORS
450鈥?12MHz CLASS C MOBILE APPLICATIONS
鈥?CLASS C TRANSISTOR
鈥?FREQUENCY 470MHz
鈥?VOLTAGE 12.5V
鈥?POWER OUT 10.0W
鈥?POWER GAIN 6.0dB
鈥?EFFICIENCY 60%
鈥?COMMON EMITTER
DESCRIPTION
The 2N5946 S a 12.5V epitaxial silicon NPN planar transLator desIgned pilnaHly for UHF comnuntl颅 ons. This device utilizes improved metalliration to achIeve Infinite VSWR at rated operatingccriditions.
ABSOLUTE MAXIMUM RATINGS (Tcne = 25CC)
THERMAL DATA
ELECTRICAL CHARACTERISTICS (T. = 25CC) STATIC
DYNAMIC
APPLICATION INFORMATION (typicaJ curves)
POWER OUTPUT VS POWER INPUT POWER OUTPUT VS FREQUENCY
I I. 鈥?
鈥?鈥? 鈥?鈥?鈥?CAPACITANCE VS V0LTASE
IMPEDANCE INFORMATION
ZIN 鈥?1.6 .j2.2E1 F = 470MHz 12V
ZOIJT = 6.0- jO34c VGE
PC 10.0W
47OMHr TEST CIRCUIT LAYOUT
2115946
PACKAGE MECHANICAL DATA
28a 4LSTUD

AP3310H datasheet

Fri, 11 May 2012 19:01:54 -0400

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AP3310H/J
Advanced Power P-CHANNEL ENHANCEMENT MODE
Electronics Corp. POWER MOSFET
鈻?Simple Drive Requirement
D BVDSS -20V
鈻?2.5V Gate Drive Capability RDS(ON) 150m惟
ID -10A
Description
The Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching,
, low on-resistance and cost-effectiveness.
G D S
TO-252(H)
This device is suited for low voltage and battery power applications.
D S TO-251(J)
Absolute Maximum Ratings
Parameter
Rating
Drain-Source Voltage
Gate-Source Voltage
ID@TA=25鈩?Continuous Drain Current, VGS @ 10V
ID@TA=100鈩?Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
PD@TA=25鈩?Total Power Dissipation
Linear Derating Factor
Storage Temperature Range
-55 to 150
Operating Junction Temperature Range
-55 to 150
Thermal Data
Parameter
Rthj-c
Thermal Resistance Junction-case Max.
Rthj-a
Thermal Resistance Junction-ambient Max.
Data and specifications subject to change without notice 201225023
AP3310H/J
Electrical Characteristics@T =25o
C(unless otherwise specified)
Parameter
Test Conditions
Drain-Source Breakdown Voltage
VGS=0V, ID=-250uA
螖BVDSS/螖Tj
Breakdown Voltage Temperature Coefficient
Reference to 25鈩? ID=-1mA
RDS(ON)
Static Drain-Source On-Resistance
VGS=-4.5V, ID=-2.8A
VGS=-2.5V, ID=-2.0A
VGS(th)
Gate Threshold Voltage
VDS=VGS, ID=-250uA
Forward Transconductance
VDS=-5V, ID=-2.8A
Drain-Source Leakage Current (Tj=25 C)
VDS=-20V, VGS=0V
Drain-Source Leakage Current (Tj=150 C)
VDS=-16V, VGS=0V
Gate-Source Leakage
VGS= 卤 12V
Total Gate Charge
ID=-2.8A VDS=-6V
VGS=-5V
Gate-Source Charge
Gate-Drain ("Miller") Charge
td(on)
Turn-on Delay Time
VDS=-6V ID=-1A
RG=6惟,VGS=-5V
Rise Time
td(off)
Turn-off Delay Time
Fall Time
Input Capacitance
VGS=0V VDS=-6V
f=1.0MHz
Output Capacitance
Reverse Transfer Capacitance
Source-Drain Diode
Parameter
Test Conditions
Continuous Source Current ( Body Diode )
VD=VG=0V , VS=-1.2V
Pulsed Source Current ( Body Diode ) 1
Forward On Voltage
Tj=25鈩? IS=-10A, VGS=0V
1.Pulse width limited by safe operating area.
2.Pulse width <300us , duty cycle <2%.
T C =25 C
V GS = -2.0V
T C =150
o C -4.5V
V GS = -2.0V
0.0 2.5 5.0 7.5 10.0
-V DS , Drain-to-Source Voltage (V)
0 2 4 6 8
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics
I D = -2.8A T C =25 鈩?I D = -2.8A V GS = -4.5V
0 2 4 6 8 10
-V GS (V)
-50 0 50 100 150
T j , Junction Temperature ( C)
Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance
v.s. Junction Temperature
25 50 75 100 125 150
0 50 100 150
T c , Case Temperature ( C)
T c , Case Temperature ( C)
Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation
Case Temperature
Duty Factor = 0.5
Single Pulse
T C =25 掳C Single Pulse
Duty Factor = t/T
Peak Tj = PDM x Rthjc + TC
1 10 100
-V DS (V)
0.00001 0.0001 0.001 0.01 0.1 1
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance
I D =-2.8A V DS =-6V
f=1.0MHz
0 2 4 6 8
Q G , Total Gate Charge (nC)
1 3 5 7 9 11 13
-V DS (V)
Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics
T j =150 C
T j =25 C
0.3 0.5 0.7 0.9 1.1 1.3 1.5
-50 0 50 100 150
-V SD (V)
T j , Junction Temperature (
Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage v.s.
Reverse Diode Junction Temperature
TO THE OSCILLOSCOPE
0.3 x RATED VDS
10% VGS
td(on) tr td(off) tf
Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform
TO THE OSCILLOSCOPE
0.3 x RATED VDS
QGS QGD
-1~-3mA
Charge Q
Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform

AD8620BRZ datasheet

Thu, 10 May 2012 13:07:19 -0400

product details:http://www.utsource.net/7665A.html
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The data to be read in conjunction with the Hydrogen
Thyratron Preamble.
DESCRIPTION
The 7665A is a rugged hydrogen thyratron designed for use in compact military and civil radars. It has a ceramic envelope with a mounting flange and flying lead connections.
It features low jitter and low anode delay time and is suitable for use at high pulse repetition rates; it can switch peak powers up to 3 MW. The tube will operate over an ambient temperature range of 755 to +130 8C. A hydrogen reservoir is incorporated.
This tube was designed to comply with, and is electrically tested to, MIL-E-1/1485D.
Peak forward anode voltage .
kV max
Peak inverse anode voltage .
kV max
Peak anode current . . .
Average anode current . .
mA max
Rate of rise of anode current
A/ms max
Anode heating factor . . .
VApps max
GENERAL
Electrical
Cathode (connected internally
Tube heating time (minimum) . . . . . 3.0 min
Mechanical
Seated height . . . . . . 63.5 mm (2.500 inches) max
Clearance required below
mounting flange . . . . . . 25.4 mm (1.000 inch) min
Overall diameter
(mounting flange) . . . 57.15 mm (2.250 inches) max Net weight . . . . . . . 160 g (0.35 pound) approx Mounting position . . . . . . . . . . . . . any Base . . . . . . . . . . . . . flange mounting
Cooling . . . . . . . . . . . natural or forced-air
When operating at maximum anode dissipation, forced-air cooling up to 0.14 m3/min (5 ft3/min) should be directed into the anode cup.
7665A Hydrogen-Filled Ceramic Thyratron
PULSE MODULATOR SERVICE MAXIMUM AND MINIMUM RATINGS (Absolute values)
Min Max
Peak forward anode voltage
(see note 1) . . . . . . . . . 鈥? 16 kV Peak inverse anode voltage (see note 2) . 鈥? 16 kV Peak anode current . . . . . . . 鈥? 350 A Average anode current . . . . . . 鈥? 500 mA Rate of rise of anode current
(see note 3) . . . . . . . . . 鈥?2000 A/ms
Anode heating factor . . . . . . . 鈥?5 x 109 VApps
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU, UK Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 e-mail: Internet: Holding Company: e2v technologies plc
e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail:
# e2v technologies (uk) limited 2005 A1A-7665A Issue 5, November 2005
282G/2639
MAXIMUM AND MINIMUM RATINGS
(Continued)
Min Max
Unloaded grid drive pulse voltage
(see note 4) . . . . Grid pulse duration . . Rate of rise of grid pulse
(see note 3) . . . . . . . . 300 鈥? V/ms Peak inverse grid voltage . . . . . 鈥? 200 V Forward impedance of
grid drive circuit . . . . . . . 50 500 O
Heaters
Cathode heater voltage . . . . . . 6.3 + 7.5% V Reservoir heater voltage . . . . . . 6.3 + 7.5% V Tube heating time . . . . . . . . 3.0 鈥? min
Environmental
Environmental performance . . . . . . . see note 5
Ambient temperature . . . . . . 755 +130 8C Altitude . . . . . . . . . . . 鈥? 3 km
鈥? 10 000 ft
CHARACTERISTICS
Min Typical Max
Critical DC anode voltage for
conduction (see note 6) . . . 鈥? 0.4 1.0 kV Anode delay time
(see notes 6 and 7) . . . . . 鈥?0.25 0.4 ms
Anode delay time drift
(see notes 6 and 8) . . . . . 鈥? 0.05 0.1 ms Time jitter (see notes 6 and 9) . . 鈥? 3.0 5.0 ns Heater current (at 6.3 V) .
Reservoir current (at 6.3 V) .
1. This is the maximum forward hold-off voltage imposed on the thyratron in a pulse modulator circuit. Tubes are tested at 18 kV peak forward anode voltage with the charging reactor inductance and pulse forming network capacitance resonant at 1000 pps For instantaneous starting applications the maximum permissible peak forward voltage is 16 kV; this must not be reached in less than 0.04 s and there must be no overshoot.
2. In pulsed operation the peak inverse anode voltage, exclusive of a spike of 0.05 ms maximum duration, must not exceed 5.0 kV during the first 25 ms after the pulse.
3. This rate of rise refers to that part of the leading edge of the pulse between 25% and 75% of the pulse amplitude.
4. Measured with respect to cathode potential.
5. The tube has been designed to withstand the following tests:
(a) Vibration 鈥?Vibrated at 10 g in each of 3 planes through the range 10 to 50 Hz and back again to 10 Hz in 10 minutes whilst looking for resonances in the range 0 to
blows in each plane.
© High Temperature Test 鈥? Tested at an ambient temperature of 150 8C under normal operating conditions for 5 hours.
6. The typical figures are obtained on test using conditions of minimum grid drive. Improved performance can be expected by increasing the grid drive.
7. The time interval between a point on the leading edge of the unloaded grid pulse at 25% of the pulse amplitude and the point where anode conduction takes place.
8. Taken as the drift in delay time over an 8-minute run at full ratings between the second and tenth minutes of operation.
9. The variation of firing time measured at 50% of current pulse amplitude.
HEALTH AND SAFETY HAZARDS
e2v technologies hydrogen thyratrons are safe to handle and operate, provided that the relevant precautions stated herein are observed. e2v technologies does not accept responsibility for damage or injury resulting from the use of electronic devices it produces. Equipment manufacturers and users must ensure that adequate precautions are taken. Appropriate warning labels and notices must be provided on equipments incorporating e2v technologies devices and in operating manuals.
High Voltage
Equipment must be designed so that personnel cannot come into contact with high voltage circuits. All high voltage circuits and terminals must be enclosed and fail-safe interlock switches must be fitted to disconnect the primary power supply and discharge all high voltage capacitors and other stored charges before allowing access. Interlock switches must not be bypassed to allow operation with access doors open.
X-Ray Radiation
All high voltage devices produce X-rays during operation and may require shielding. The X-ray radiation from hydrogen thyratrons is usually reduced to a safe level by enclosing the equipment or shielding the thyratron with at least 1.6 mm ( 1/16 inch) thick steel panels.
Users and equipment manufacturers must check the radiation level under their maximum operating conditions.
7665A, page 2 # e2v technologies
OUTLINE
(All dimensions without limits are nominal)
ANODE CONNECTION FITTED WITH 8-32 UNC SCREW
MOUNTING FLANGE F SEE NOTE 1
Inch dimensions have been derived from millimetres.
SEE NOTE 2 D
SEE NOTE 3
RESERVOIR HEATER LEAD (RED) L LONG, TAG TO FIT 1M TERMINAL
GRID LEAD (GREEN) L LONG TAG TO FIT 1M TERMINAL
Outline Notes
1. The mounting flange is the connection for the cathode, cathode heater return and reservoir heater return.
2. A minimum clearance of 25.4 mm (1.000 inch)
must be allowed below the mounting flange.
3. Where e2v technologies gives prior agreement to the use of alternative lead/mounting ar- rangements on these posts, great care must be taken to avoid damaging the threads and the metal/ceramic joints. A flat wrench must be used to hold the nut nearest the ceramic while a torque wrench, set to a value of less than
0.046 kg-m (4 lb-in), is used on the other nut.
CATHODE HEATER LEAD (YELLOW)
L LONG, TAG TO FIT 1M TERMINAL 4 HOLES 1H
EQUISPACED ON J PCD
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.
# e2v technologies
Printed in England
7665A, page 3

stan van gundy tom brady

Tue, 08 May 2012 22:11:37 -0400

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BQ2057WSNTR datasheet

Tue, 08 May 2012 06:49:18 -0400

product details:http://www.utsource.net/BQ2058CSN-C5.html
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Lithium Ion Pack Supervisor for 3- and 4-Cell Packs
Features
鉃?Protects and individually moni- tors three or four Li-Ion series cells for overvoltage, undervolt- age
鉃?Monitors pack for overcurrent
鉃?Designed for battery pack inte- gration
鉃?Minimal external components
鉃?Drives external FET switches
鉃?Selectable overvoltage (V OV )
thresholds
- Mask-programmable by
Unitrode
- Standard version鈥?.25V
鉃?Supply current: 25碌A typical
鉃?Sleep current: 0.7碌A typical
鉃?16-pin 150-mil narrow SOIC
General Description
The bq2058 Lithium Ion Pack Super- visor is designed to control the charge and discharge cell voltages for three or four lithium ion (Li-Ion) series cells, accommodating battery packs contain- ing series/parallel configurations. The low operating current does not over- discharge the cells during periods of storage and does not significantly in- crease the system discharge load. The bq2058 can be part of a low-cost Li-Ion charge control system within the bat- tery pack.
The bq2058 controls two external FETs to limit the charge and discharge poten- tials. The bq2058 allows charging when each individual cell voltage is below VOV (overvoltage limit). If the voltage on any cell exceeds VOV for a user-configurable delay period (tOVD), the CHG pin is driven high, shutting off charge to the battery pack. This safety feature pre-
vents overcharge of any cell within the battery pack. After an overvolt- age condition occurs, each cell must fall below VCE (charge enable voltage) for the bq2058 to re-enable charging.
The bq2058 protects batteries from overdischarge. If the voltage on any cell falls below VUV (undervoltage limit) for a user-configurable delay pe- riod (tUVD), the DSG output is driven high, shutting off the battery dis- charge. This safety feature prevents overdischarge of any cell within the battery pack.
The bq2058 also stops discharge on detection of an overcurrent condition, such as a short circuit. If an overcur- rent condition occurs for a user- configurable delay period (tOCD), the DSG output is driven high, disconnect- ing the load from the pack. DSG re- mains high until removal of the short circuit or overcurrent condition.
Pin Connections
Pin Names
BAT4N 5
BAT3N 6
BAT2N 7
BAT1N 8
15 NSEL
9 BAT1P
CHG Charge control output
CTL Pack disable input VSS Low potential input CSL Current sense low-side
BAT4N Battery 4 negative input BAT3N Battery 3 negative input BAT2N Battery 2 negative input
DSG Discharge control output NSEL 3- or 4-cell selection UVD Undervoltage delay input OVD Overvoltage delay input OCD Overcurrent delay input VCC High potential input
CSH Current sense high-side
16-Pin Narrow SOIC
PN205801.eps
BAT1N Battery 1 negative input
BAT1P Battery 1 positive input
Pin Descriptions
CHG Charge control output
This push-pull output controls the charge path to the battery pack. Charging is al- lowed when low.
CTL Pack disable input
When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal opera- tion, the CTL pin is low.
VSS Low potential input
CSL Overcurrent sense low-side input
This input is connected between the low-side discharge FET (or sense resistor) and BAT4N to enable overcurrent sensing in the battery pack鈥檚 ground path.
BAT4N Battery 4 negative input
This input is connected to the negative termi- nal of the cell designated BAT4 in Figure 2.
BAT3N Battery 3 negative input
This input is connected to the negative terminal of the cell designated BAT3 in Figure 2.
BAT2N Battery 2 negative input
This input is connected to the negative termi- nal of the cell designated BAT2 in Figure 2.
BAT1N Battery 1 negative input
This input is connected to the negative termi- nal of the cell designated BAT1 in Figure 2.
This input is connected to BAT1P in a three- cell configuration.
DSG Discharge control output
This push-pull output controls the discharge path to the battery pack. Discharge is al- lowed when low.
NSEL Number of cells input
This input selects the number of series cells in the pack. NSEL should connect to VCC for four cells and to VSS for three cells.
UVD Undervoltage delay input
This input uses an external capacitor to VCC
to set the undervoltage delay timing.
OVD Overvoltage delay input
This input uses an external capacitor to VCC
to set the overvoltage delay timing.
OCD Overcurrent delay input
This input uses an external capacitor to VCC
to set the overcurrent delay timing.
VCC High potential input
CSH Overcurrent sense high-side input
This input is connected between the high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack鈥檚 positive supply path.
BAT1P Battery 1 positive input
This input is connected to the positive terminal of the cell designated BAT1 in Figure 2.
Table 1. Pin Configuration for 3- and 4-Series Cells
Number of Cells
Configuration Pins
Battery Pins
3 cells
BAT1N tied to BAT1P
NSEL = VSS
BAT1N 鈥?Positive terminal of first cell
BAT2N 鈥?Negative terminal of first cell
BAT3N 鈥?Negative terminal of second cell
BAT4N 鈥?Negative terminal of third cell
4 cells
NSEL = VCC
BAT1P 鈥? Positive terminal of first cell
BAT1N 鈥?Negative terminal of first cell
BAT2N 鈥?Negative terminal of second cell
BAT3N 鈥?Negative terminal of third cell
BAT4N 鈥?Negative terminal of fourth cell
Cell Inputs
B1P B1N
Number of Cells Select
B2N B3N B4N
Pin 15
D Overcharge
Chip Negative
Any_Above_VOV
CK Edge Out QB
D Q Non-Retrigger
Charge Control
Sel3 CK QB
Pin 13 OVD
Capacitor
Oneshot
Output
Sel2 CK QB
Discharge Off Delay Capacitor Input
All_Below_VCE
Sel1 CK QB
Sel4 CK
Any_Below_VUV
Edge Out
QB Non-Retrigger
Sel3 CK
Capacitor
Oneshot
Discharge Control
Sel2 CK
Charge Off Delay Capacitor Input
Sense High-side Input
Pin 10 CSH
Sense Low-side Input
B4N +
Edge Out
CK Q QB
Overcurrent
Sel4 CK
Overcurrent Delay
Non-Retrigger
Sel3 QB
Sel2 CK QB
CSH B1P CSL
Capacitor Input
Capacitor
Oneshot
Sel1 CK QB
External Output Control
Figure 1. Block Diagram
Functional Description
Figure 1 is a block diagram outlining the major compo- nents of the bq2058. Figure 2 shows a 3- or 4-cell pack supervisor circuit. The following sections detail the vari- ous functional aspects of the bq2058.
Thresholds
The bq2058 monitors the lithium ion pack for the condi- tions listed below. Shown with these conditions are the respective thresholds used to determine if that condition exists:
鈻? Overvoltage (VOV)
鈻? Undervoltage (VUV)
鈻? Overcurrent (VOCH, VOCL)
鈻? Charge Enable (VCE)
鈻? Charge Detect (VCD)
The bq2058 samples a cell every 40ms (typical). Every sample is a fully differential measurement of each cell. During this sample period, the bq2058 compares the measurements with these thresholds to determine if any of the these conditions exist: VOV, VUV, and VCE.
Overcurrent and charge detect are conditions that are not sampled, but are continuously monitored.
Initialization
On initial power-up, such as connecting the battery pack for the first time to the bq2058, the bq2058 enters the low-power sleep mode, disabling the DSG output. It is recommended that a top to bottom cell connection be made at pack assembly for proper initializa- tion. A charging supply must be applied to the bq2058 circuit to enable the pack. See Low-Power Sleep Mode and Charge Detect sections.
* See note 1.
ZVP3306F
* See note 2.
Si4435DY
Si4435DY
11 VCC
U1 bq2058
NSEL 15
OVD 13
R4 C1
9 BAT1P
UVD 14
0.001uF
8 BAT1N
7 BAT2N
OCD 12
DSG 16
R5 C2
0.001uF
6 BAT3N
5 BAT4N
CSH 10
CHG 1
R7 C3
3 VSS
CTL 2
0.001uF
CSL 4
R8 C4
0.001uF
1. For automatic short circuit recovery.
2. Remove R11 for 4-cell. Remove R10 and connect
B1P to B1N for 3-cells.
Figure 2. 3- or 4-Cell Li-Ion Battery Pack Supervisor
Low-Power Sleep Mode
The bq2058 enters the low-power sleep mode in two dif- ferent ways:
1. On initial power-up.
2. After the detection of an undervoltage condi- tion鈥揤UV.
When the bq2058 enters the low-power sleep mode, DSG is driven high and the device consumes 0.7碌A (typical). The bq2058 only comes out of low-power sleep mode when a valid charge-detect condition exists.
Charge Detect
The bq2058 continuously monitors for a charge-detect con- dition. A valid charge-detect condition exists when either of the conditions are true:
CSL < BAT4N - 70mV (VCD) CSH > BAT1P + 70mV (VCD)
A valid charge-detect enables the DSG output, allowing charging of the lithium ion cells. This is accomplished by applying the charging supply to the pack.
Undervoltage
Undervoltage (or overdischarge) protection is asserted when any cell voltage drops below the VUV threshold and remains below the V UV threshold for a time exceeding a user-configurable delay (tUVD). The DSG output is driven high disabling the discharge of the pack. The bq2058 then enters the low-power sleep mode.
Overvoltage
Overvoltage (or overcharge) protection is asserted when any cell voltage exceeds the VOV threshold and remains above the VOV threshold for a time exceeding a user- configurable delay (tOVD). The CHG pin is driven high, disabling charge into the battery pack. Charging is dis- abled until a valid charge enable exists. See Charge En- able section.
Important note: If any battery pin floats (BAT1P, BAT1N鈥?N), the bq2058 assumes an overvoltage has occurred.
Because of different manufacturers specifications for overvoltage thresholds, the bq2058 can be available with different VOV options. Table 2 summarizes these differ- ent voltage thresholds.
Table 2. Overvoltage Threshold Options
Part No.
VOV Limit
bq2058
bq2058C
bq2058D
bq2058G*
4.375V
bq2058R
bq2058W
The overvoltage threshold limits are programmed at Unitrode. The bq2058 is the standard option that is more readily available for sampling and prototyping purposes. Please contact Unitrode for other voltage threshold and tolerance options.
Charge Enable
A valid charge enable indicates that an overvoltage (overcharge) condition no longer exists and that the pack is ready to accept further charge. Once overvoltage protection is asserted, charging will not be enabled un- til all cell voltages fall below VCE. The VCE threshold is a function of VOV, and changes with different VOV lim- its.
VCE = VOV - 150mV
Overcurrent
The bq2058 detects an overcurrent (or short circuit) con- dition only in the discharge direction. Overcurrent pro- tection is asserted when either of the conditions occurs and remain for a time exceeding a user-configurable de- lay (tOCD):
CSL > BAT4N + VOCL
CSH < BAT1P - VOCH
VOCL = 160mV (low-side detect) VOCH = 160mV (high-side detect)
When either of these conditions occurs, DSG is driven high, disconnecting the load from the pack. DSG re- mains high until both of the voltage conditions are false, indicating removal of the short-circuit condition. The user can facilitate clearing these conditions by inserting the battery pack into a charger.
The low-side overcurrent sense can be disabled by con- necting CSL to BAT4N. This ensures that CSL is never greater than BAT4N. If low-side detection is disabled, high-side detection must be used with CSH.
The FETs in the charge/discharge path controlled by the CHG and DSG pins affect the overcurrent level. The on-resistance of these FETs need to be taken into ac- count when determining overcurrent levels.
Condition
CHG pin
DSG pin
Normal operation
Overvoltage
Undervoltage
Overcurrent
Floating battery input
Indeterminate
CTL = high
CHG and DSG States
The CHG and DSG output truth table is shown below.
The polarities of CHG and DSG are mask programmable at Unitrode. Push-pull vs. open-drain configuration is also mask-configurable at Unitrode. Please contact Unitrode for availability of these variations.
Number of Cells
The user must configure the bq2058 for three- or four- series cell operation. For a three-cell pack, NSEL should be tied directly to VSS. For a four-cell pack, NSEL should be connected directly to VCC.
Pack Disable Input鈥揅TL
The CTL pin is used to electrically disconnect the bat- tery from the pack terminals through an externally sup- plied signal. When CTL is taken high, CHG and DSG are driven high. Any load on the pack terminals will be interpreted as an overcurrent condition by the bq2058 with the overcurrent delay timer held in reset. When the CTL pin is driven low, the overcurrent delay timer is allowed to start. If the programmed delay (tOCD) is too short, the overcurrent recovery circuit, if implemented, will be unable to correct the overcurrent situation prior to the delay time-out. It is recommended that a delay time of greater than 10ms (COCD 鈮? 0.01碌F) be used if
the CTL pin function is used.
Important note: If CTL floats, it is internally pulled high making both DSG and CHG inactive, thus disabling the pack. If CTL is not used, it should be tied to VSS.
The polarity of CTL is mask programmable at Unitrode. Please contact Unitrode for other polarity options.
Protection Delay Timers
The delay time between the detection of an overcurrent, overvoltage, or undervoltage condition and the deactivation of the CHG and/or DSG outputs is user-configurable by the selection of capacitor values between VCC and OCD, OVD, and UVD pins (respectively). See Table 3 below.
The fault condition must persist through the entire de- lay period, or the bq2058 may not deactivate either FET control output.
Figure 3 shows a step-by-step event cycle for the bq2058.
Table 3. Protection Delay Timers
Protection
Feature
Capacitor from
VCC to:
Typical
Tolerance
Capacitor
Overcurrent
0.010碌F
Overvoltage
0.100碌F
Undervoltage
0.100碌F
Notes: 1. The delay time versus capacitance can be approximated by the following equations:.
For tOCD:
t(s) 鈮?1.2 鈭?C(碌f),
where C 鈮?0.001碌F
For tOVD, tUVD:
t(s) 鈮?9.5 鈭?C(碌f),
where C 鈮?0.01碌F
2. Overvoltage and undervoltage conditions are sampled by the bq2058. The delay in Table 2 is in
addition to the time required for the bq2058 to detect the violation, which may vary from 0 to
160 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously monitored and is subject to a delay of approximately 1.5ms.
0 1 2 3 4 5 6 7 8 9 10 11 12
Cell Voltage
BAT1P + 70mV (VCD)
BAT1P - 160mV (VOCH)
TD205801.eps
Figure 3. Protector Event Diagram
Event Definition:
0: The bq2058 is in the low-power sleep mode because one or more of the cell voltages are below VUV.
1: A charger is applied to the pack, causing the difference between CSH and BAT1P to become greater than 70mV. This awakens the bq2058, and the discharge pin DSG goes low.
2: One or more cells charge to a voltage equal to VOV, initiating the overvoltage delay timer.
3: The overvoltage delay time expires, causing CHG to be driven high.
4: All cell voltages fall below VCE, causing CHG to be driven low.
5: Stop charging, apply a load.
6: An overcurrent condition is detected, initiating the overcurrent delay timer.
7: The overcurrent delay time expires, causing DSG to be driven high.
8: The overcurrent condition is no longer present; DSG is driven low.
9: Pin CTL is driven high; both DSG and CHG are driven high.
10: Pin CTL is driven low; both DSG and CHG resume their normal function.
11: One or more cells fall below VUV, initiating the overdischarge delay timer.
12: Once the overdischarge delay timer expires, if any of the cells is below VUV, the bq2058 drives
DSG high and enters the low-power sleep mode.
Absolute Maximum Ratings
Parameter
Conditions
Supply voltage
Relative to VSS
Operating temperature
-30 to +70
Storage temperature
-55 to +125
TSOLDER
Soldering temperature
For 10 seconds
Maximum input current
All pins except VCC, VSS
Notes: 1 Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
2. Internal protection diodes are in place on every pin relative to VCC and VSS. See Figure 4.
Any pin
FG2058x .eps
Figure 4. Internal Protection Diodes
DC Electrical Characteristics (TA = TOPR)
Parameter
Minimum
Typical
Maximum
Conditions/Notes
Output high voltage
VCC - 0.5
IOH = 10碌A, CHG, DSG
Output low voltage
VSS + 0.5
IOL = 10碌A, CHG, DSG
Operating voltage
VCC relative to VSS
Input low voltage
VSS + 0.5
Pin CTL
Input high voltage
VSS + 2.0
Pin CTL
Input low voltage
VSS + 0.5
Pin NSEL
Input high voltage
VCC - 0.5
Pin NSEL
Active current
Sleep current
DC Thresholds (TA = TOPR)
Parameter
Tolerance
Conditons
Overvoltage threshold
(See Figure 5)
See note 1
For bq2058G only
See note 3
Table 2
Customer option
Charge enable threshold
VOV - 150mV
VOV - 200mV
For bq2058W only
Undervoltage threshold
卤100mV
卤100mV
For bq2058W only
Overcurrent detect high-side
Overcurrent detect low-side
Charge detect threshold
-60mV, +80mV
Overvoltage delay threshold
COVD = 0.100碌F, TA = 30掳C See note 2
Undervoltage delay threshold
CUVD = 0.100碌F, TA = 30掳C See note 2
Overcurrent delay threshold
COCD = 0.01碌F, TA = 30掳C
Notes: 1. Standard device. Contact Unitrode for different thresholds and tolerance options.
2. Does not include cell sampling delay, which may add up to 160ms of additional delay until the condition is detected.
3. bq2058G is designed only for 3-cell applications.
Impedance
Parameter
Minimum
Typical
Maximum
Input impedance
Pins BAT1P, BAT1N-4N, CSH, CSL
-20 -10 0 10 20 30 40 50 60 70
TA 鈥?Free-Air Temperature 鈥?藲C
Gr2058.eps
Figure 5. bq2058 4.25V Overvoltage Threshold vs.
Free-Air Temperature
Data Sheet Revision History
Change No.
Page No.
Description
Nature of Change
1, 2, 5
PACK+, PACK-
Pins renamed to CSH and CSL respectively
Pin description
Added CSH/CSL description
Block diagram
Update Block diagram
Figure 2
Update typical application circuit
Configuration description
Correction to description
Overcurrent limits
Was: VOCH = 150mV 卤 25mV VOCL = 85mV 卤 25mV
Is: VOCH = 160mV 卤 25mV VOCL = 100mV 卤 25mV
Figure 3
Update Event diagram
DC threshold
Was: VOCH = 150mV 卤 25mV VOCL = 100mV 卤 80mV VCD = 70mV -60, +50mV
Is: VOCH = 160mV 卤 25mV
VOCL = 100mV 卤 25mV
VCD = 70mV -60, +80mV
1, 3, 5
High-side overcurrent monitored
Was: Between VCC and CSH, Is: Between BAT1P and CSH
Overvoltage threshold options
Added bq2058R
Overcurrent limit
Was: VOCL = 100mV, Is: VOCL = 150mV
Figure 2
Corrected schematic
Protection Delay Times
Was: tOCD = 10ms 卤30% tOVD = 800ms 卤30% tUVD = 800ms 卤40%
Is: tOCD = 12ms 卤40% tOVD = 950ms 卤40% tUVD = 950ms 卤40%
Overcurrent limits
Was: VOCH = 160mV 卤25mV VOCL = 150mV 卤25mV
Is: VOCH = 160mV 卤35mV
VOCL = 160mV 卤35mV
Overvoltage threshold Charge enable threshold Undervoltage threshold
Added bq2058W
DC electrical characteristics
Was: Minimum VOP = 0V, Is: Minimum VOP = 4V
Overvoltage threshold
Added bq2058C and bq2058G
Reference circuit amended
Moved D1 to new location
Notes: Change 1 = Feb. 1997 B changes from Jan. 1997 A. Change 2 = April 1997 C changes from Feb. 1997 B.
Change 3 = June 1997 D changes from April 1997 C. Change 4 = July 1997 E changes from June 1997 D. Change 5 = Feb. 1998 F changes from July 1997 E. Change 6 = May 1998 G changes from Feb. 1998 F. Change 7 = June 1998 H changes from May 1998 G.
Change 8 = Jan. 1999 I changes from June 1998 H.
SN: 16-Pin SN (0.150" SOIC)
16-Pin SN (0.150" SOIC)
Ordering Information
bq2058 XXXX
Standard Device:
Blank = Standard device
XXXX = Customer code assigned by Benchmarq
Package Option:
SN = 16-pin narrow SOIC
Overvoltage Threshold
Blank = 4.25V (Standard device)
Contact Factory for availability of other thresholds
Device:
bq2058 Lithium Ion Pack Supervisor
Package Devices
VOV Threshold
16-pin Narrow SOIC (SN)
-30掳C To
bq2058WSN
bq2058MSN
bq2058FSN
4.225V
bq2058KSN
bq2058SN
4.325V
bq2058CSN
bq2058DSN
bq2058RSN
bq2058JSN
4.375V
bq2058GSN
Notes: bq2058SN is Standard Device.
Contact factory for availability of other thresholds and tolerances.
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI鈥檚 standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (鈥淐RITICAL APPLICATIONS鈥?. TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER鈥橲 RISK.
In order to minimize risks associated with the customer鈥檚 applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI鈥檚 publication of information regarding any third party鈥檚 products or services does not constitute TI鈥檚 approval, warranty or endorsement thereof.
Copyright 飪?1999, Texas Instruments Incorporated

ZTX750 datasheet

Mon, 07 May 2012 20:14:09 -0400

product details:http://www.utsource.net/ZTX750.html
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PNP SILICON PLANAR
MEDIUM POWER TRANSISTORS
ZTX75O ZTX75I
ISSUE 2 - JULY 94
FEATURES
* 60 Volt VCEO
* 2 Amp continuous current
* Low saturation voltage
* Ptot= 1 Watt
ABSOLUTE MAXIMUM RATINGS.
E-Line
TO92 Compatible
PARAMETER SYMBOL ZTX750 ZTX751 UNIT Collector-Base Voltage VCBO -60 -80 V
Collector-Emitter Voltage VCEO -45 -60 V
Emitter-Base Voltage VEBO -5 V Peak Pulse Current ICM -6 A
Continuous Collector Current IC -2 A
Power Dissipation: at Tamb=25掳C
derate above 25掳C
Ptot 1
Operating and Storage Temperature Range Tj:Tstg -55 to +200 掳C
ELECTRICAL CHARACTERISTICS (at Tamb = 25掳C unless otherwise stated).
ZTX750 ZTX751
PARAMETER SYMBOL MIN. TYP. MAX. MIN. TYP. MAX. UNIT CONDITIONS.
Collector-Base Breakdown Voltage
Collector-Emitter Breakdown Voltage
Emitter-Base Breakdown Voltage
V(BR)CBO -60 -80 V IC=-100 A V(BR)CEO -45 -60 V IC=-10mA
V(BR)EBO -5 -5 V IE=-100 A
Collector Cut-Off
Current
ICBO -0.1
A VCB=-45V A VCB=-60V
A VCB=-45V,Tamb=100掳C
VCB=-60V,Tamb=100掳C
Emitter Cut-Off
Current
IEBO -0.1 -0.1 A VEB=-4V
Collector-Emitter
Saturation Voltage
VCE(sat) -0.15
-0.3 V
-0.5 V
IC=-1A, IB=-100mA IC=-2A, IB=-200mA
Base-Emitter Saturation Voltage
VBE(sat) -0.9 -1.25 -0.9 -1.25 V IC=-1A, IB=-100mA
ZTX75O ZTX75I
ELECTRICAL CHARACTERISTICS (at Tamb = 25掳C unless otherwise stated).
ZTX750 ZTX751
PARAMETER SYMBOL
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT CONDITIONS.
Transition
Frequency
fT 100 140 100 140 MHz IC=-100mA, VCE=-5V
f=100MHz
Switching Times ton 40 40 ns IC=-500mA, VCC=-10V IB1=IB2=-50mA
Capacitance
toff 450 450 ns
Cobo 30 30 pF VCB=10V f=1MHz
*Measured under pulsed conditions. Pulse width=300 s. Duty cycle 2%
THERMAL CHARACTERISTICS
PARAMETER SYMBOL MAX. UNIT
Thermal Resistance:Junction to Ambient1
Junction to Ambient2
Junction to Case
Rth(j-amb)1
Rth(j-amb)2t
Rth(j-case)
t Device mounted on P.C.B. with copper equal to 1 sq. Inch minimum.
D=1 (D.C.)
D=t1/tP
Single Pulse
-40 -20 0 20 40 60 80 100 120 140 160 180 200
0.0001
1 10 100
T -Temperature (掳C)
Pulse Width (seconds)
Derating curve
Maximum transient thermal impedance
ZTX75O ZTX75I
TYPICAL CHARACTERISTICS
IC/IB=10
td tr tf ns
500 td tf
IB1=IB2=IC/10
0.01 0.1
40 200
20 100
IC - Collector Current (Amps)
VCE(sat) v IC
IC - Collector Current (Amps)
Switching Speeds
IC/IB=10
0.01 0.1 1
0.0001 0.001
0.1 1 10
IC - Collector Current (Amps)
hFE v IC
IC - Collector Current (Amps)
VBE(sat) v IC
Single Pulse Test at Tamb=25掳C
0.0001 0.001
0.1 1 10
1 10 100
IC - Collector Current (Amps)
VBE(on) v IC
VCE - Collector Voltage (Volts)
Safe Operating Area

PMB8875 datasheet

Sat, 05 May 2012 13:17:21 -0400

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0007200TDSHTNAA0OSESPEop,L, SILICON APRYRIPLE SIFFU150 MESA TYPE
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MBRD1035CTL datasheet

Wed, 02 May 2012 11:34:03 -0400

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SEMICONDUCTOR TECHNICAL DATA
Order this document by MBRD1035CTL/D
DPAK Power Surface Mount Package
. . . employing the Schottky Barrier principle in a large area metal鈥搕o鈥搒ilicon power diode. State of the art geometry features epitaxial construction with oxide passivation and metal overlay contact. Ideally suited for low voltage, high frequency switching power supplies, free wheeling diode and polarity protection diodes.
飩? Highly Stable Oxide Passivated Junction
飩? Guardring for Stress Protection
飩? Matched dual die construction 鈥?May be Paralleled for High Current Output
飩? High dv/dt Capability
飩? Short Heat Sink Tap Manufactured 鈥?Not Sheared
飩? Very Low Forward Voltage Drop
飩? Epoxy Meets UL94, VO at 1/8鈥?Mechanical Characteristics:
飩? Case: Epoxy, Molded
飩? Weight: 0.4 gram (approximately)
飩? Finish: All External Surfaces Corrosion Resistant and Terminal Leads are
Readily Solderable
飩? Lead and Mounting Surface Temperature for Soldering Purposes:
260飩癈 Max. for 10 Seconds
飩? Shipped in 75 units per plastic tube
飩? Available in 16 mm Tape and Reel, 2500 units per Reel, Add 鈥淭4鈥欌€?to Suffix part #
飩? Marking: B1035CL
MAXIMUM RATINGS
SCHOTTKY BARRIER RECTIFIER
10 AMPERES
35 VOLTS
CASE 369A鈥?3
Symbol
Peak Repetitive Reverse Voltage Working Peak Reverse Voltage DC Blocking Voltage
VRRM VRWM VR
Average Rectified Forward Current Per Leg
(At Rated VR, TC = 115飩癈) Per Package
Peak Repetitive Forward Current Per Leg
(At Rated VR, Square Wave, 20 kHz, TC = 115飩癈)
Non鈥揜epetitive Peak Surge Current Per Package
(Surge applied at rated load conditions, halfwave, single phase, 60 Hz)
Storage / Operating Case Temperature
Tstg, Tc
鈥?5 to +125
Operating Junction Temperature
鈥?5 to +125
Voltage Rate of Change (Rated VR, TJ = 25飩癈)
10,000
THERMAL CHARACTERISTICS
Thermal Resistance 鈥?Junction to Case Per Leg
Thermal Resistance 鈥?Junction to Ambient (1) Per Leg
(1) Rating applies when using minimum pad size, FR4 PC Board
SWITCHMODE is a trademark of Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
飪?Motorola, Inc. 1998
ELECTRICAL CHARACTERISTICS
Maximum Instantaneous Forward Voltage(2), see Figure 2 Per Leg
IF = 5 Amps, TJ = 25飩癈 IF = 5 Amps, TJ = 100飩癈 IF = 10 Amps, TJ = 25飩癈 IF = 10 Amps, TJ = 100飩癈
Maximum Instantaneous Reverse Current, see Figure 4 Per Leg
(VR = 35 V, TJ = 25飩癈) (VR = 35 V, TJ = 100飩癈) (VR = 17.5 V, TJ = 25飩癈) (VR = 17.5 V, TJ = 100飩癈)
(2) Pulse Test: Pulse Width 飩?250 s, Duty Cycle 飩?2.0%.
TYPICAL CHARACTERISTICS
TJ = 125飩癈
10 TJ = 100飩癈
10 TJ = 125飩癈
TJ = 25飩癈
TJ = 鈥?40飩癈
TJ = 25飩癈
TJ = 100飩癈
0.70 0.90
0.70 0.90
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 1. Typical Forward Voltage Per Leg Figure 2. Maximum Forward Voltage Per Leg
TJ = 125飩癈
100E鈥?
TJ = 125飩癈
TJ = 100飩癈
TJ = 100飩癈
TJ = 25飩癈
100E鈥?
TJ = 25飩癈
Figure 3. Typical Reverse Current Per Leg
Figure 4. Maximum Reverse Current Per Leg
SQUARE WAVE (50% DUTY CYCLE)
Ipk/Io =
Ipk/Io = 5
Ipk/Io = 10
Ipk/Io = 20
freq = 20 kHz
Ipk/Io = 5
Ipk/Io = 10
Ipk/Io = 20
SQUARE WAVE
(50% DUTY CYCLE) dc
Ipk/Io =
0 20 40
60 80 100
3.0 4.0 5.0 6.0 7.0 8.0
TL, LEAD TEMPERATURE (飩癈)
IO, AVERAGE FORWARD CURRENT (AMPS)
Figure 5. Current Derating Per Leg Figure 6. Forward Power Dissipation Per Leg
TJ = 25飩癈
R JA = 48飩癈/W
R JA = 2.43飩癈/W
R JA = 25飩癈/W
R JA = 67.5飩癈/W
R JA = 84飩癈/W
0 5 10 15 20 25
0 5 10 15 20
25 30 35
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitance Per Leg
VR, DC REVERSE VOLTAGE (VOLTS)
Figure 8. Typical Operating Temperature
Derating Per Leg *
* Reverse power dissipation and the possibility of thermal runaway must be considered when operating this device under any re- verse voltage conditions. Calculations of TJ therefore must include forward and reverse power effects. The allowable operating TJ may be calculated from the equation: TJ = TJmax 鈥?r(t)(Pf + Pr) where
r(t) = thermal impedance under given conditions,
Pf = forward power dissipation, and
Pr = reverse power dissipation
This graph displays the derated allowable TJ due to reverse bias under DC conditions only and is calculated as TJ = TJmax 鈥?r(t)Pr, where r(t) = Rthja. For other power applications further calculations must be performed.
50%(DUTY CYCLE)
1.0% SINGLE PULSE
Rtjl(t) = Rtjl 飩?r(t)
0.00001
0.0001 0.001 0.01
t, TIME (s)
1.0 10 100 1000
Figure 9. Thermal Response Junction to Case (Per Leg)
1.0E+00
1.0E鈥?1
1.0E鈥?2
50% (DUTY CYCLE)
1.0E鈥?3
SINGLE PULSE
Rtjl(t) = Rtjl 飩?r(t)
1.0E鈥?4
0.00001
0.0001 0.001 0.01
t, TIME (s)
1.0 10 100
Figure 10. Thermal Response Junction to Ambient (Per Leg)
PACKAGE DIMENSIONS
鈥揟鈥? SEATING PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
F J L H
CASE 369A鈥?3
ISSUE Y
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 鈥淭ypical鈥?parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including 鈥淭ypicals鈥?must be validated for each customer application by customer鈥檚 technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
Mfax is a trademark of Motorola, Inc.
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
P.O. Box 5405, Denver, Colorado 80217. 1鈥?03鈥?75鈥?140 or 1鈥?00鈥?41鈥?447 4鈥?2鈥? Nishi鈥揋otanda, Shagawa鈥搆u, Tokyo, Japan. 03鈥?487鈥?488
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Mfax飪? 鈥?TOUCHTONE 1鈥?02鈥?44鈥?609 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System 鈥?US & Canada ONLY 1鈥?00鈥?74鈥?848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852鈥?6629298
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MPSU60 datasheet

Wed, 02 May 2012 08:18:09 -0400

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MOTORCLA Sc XSTRS/R F 12E 0 6367254 0085511 6
MOTOROLA SEMICONDUCTOR TECHNICAL DATA
-r-43 -17
MPS-U60
ANNULAR TRANSISTOR
for general鈥urpose applications requiring high break. low saturation voltages and low capacitance.
8 to NPN Type MPS.U1O
PNP SILICON HIGH VOLTAGE TRANSISTOR
MAXIMUM RATINGS
Collector Emitter Voltage
Snmbol Vatoa Ueir U
VCEO 300 Vdc
ColleororBara Voltage
Emirttr.Bane Voltage
Collector Currant 鈥? Cnnrinuoue
C 500 m.Adc E
Total Pnwer Cinriparion @ TA 2bnC Onrare above 28掳c
Total Pny.ne oieelparlon@Tc 2b掳C Oerate above 2b0C
P0 1.0
Watt S
wWl掳C C
Operarina and Stnrage Junction
Temperature Range
TiTer0 -bb to vito 掳C
THERMAL CHARACTERISTICS
Charanrerietio Spmbnl Man UnIt
Thermal Ornirtance, Junction to Cam
12.5 掳CiW
Thermal Renirrance. Junction to Ambient
RAJAI1) tab
ELECTRICAL CHARACTERISTICS ITA = 25掳C cnlern ethetwna noredi
Sambol j Mie Mac Unit
OFF CHARACTERISTICS
Collector Emitter Breakdown voitagnl2l
I 0 mAdu, Ig 0)
Collector-Bare Breakdown Voltage
I1C lOOpAdn. E 01
Emitter-Bare areabdown Vntrage
(I iOpAdn. IC = 0)
Coliecror Ccrol I Correct
lVg = 200 Vdn. l 01
Emitter Corofl Current
IVBE 30 V4. 鈥楥 = SI
ON CHARACTERISTICS
IBRlCao VIBR)EEO CBO
Vdc Vdc Vdc
.1G1-. smut:
-e -I P61.6650208
3. C0t9.tCTl]R
IcOU.6CT08 cONNECTED 10 TAO)
CC Currant Oem 121
Ic I S mAdc, VCE IS VdcI
1IC IC mAde, VCE 10 Vdcl
I1C .O5rrrAdc, VCE lSVdcI Collector-EmitterSarurarinn Voltage
IIC=2SmAdc.le =2 SmAdcl
Eaea Emitter Sarorarion Voltage
- 2SrrrAdc, lB 鈥?2.OmAdcl
VCEIM51
Vas lear I
1. LEAOSWITIIIND.ltmm{0Th)T000LQf 18118
POSITiON AT CASt. AT UA)tMtM MAIOPJAt
CONDITiON.
ON W4IMAX SN MAX A 9.14 J53 0240 0.321
8 816 I 1.24 0.200 0205
141 LOW 0.213 0022
D 039 0.53 0015 0021
F 3.19 3.33 0.125 0.131
OVNAMIC CHARACTERI5TICS
9 25480C o.TOOSSC
Current Oain鈥擝andwidth Product 12)
ltCt掳 mAde. VCE =25 Vdc,( IOOMHeI Colleotor Bane Capacitance
IVCB -2 Vdc. E =0,1- 1 0 MHeI
1T 60 鈥擳 MHe
H 3.04 4.19 0.150 0.180
028 OAt 0914 00)8
K 1103 (220 0.408 9180
2459 2553 0168 1005
N SW0SC L20080C
(1) RQJ,O, is meeeored with the denise eoldared Into e typical printed circuIt board.
121 Pulse Test: Pulse Width < 300ps, Duty Cycla 2.0%.
0 2.39J 2.69 os[oros
6 1.14 1 140 0040 I 0000
CASE 152-02
3-1 066
MOTORCLA Sc XSTRS/R F
12E 0 6367254 0085512 8
MPS-U60
r 33r,7
Tj = 1125掳C
FIGURE 1 鈥?DC CURRENT GAIN
I I I I I LIII t 鈥楾掳鈥?VCE IOVdc
.-30L I II
1.0 2.0 3.0 5.0 7.0 10 20 30 50 00 100
IC,00LLECTOR CURRENT (mA)
FIGURE 2鈥?CAFACITANCES FIGURE 3鈥擟URRENT-GAIN鈥擝ANDWIDTH FRODUCT
100 100
Tj=25掳C
I 00 VCE2RVdC
1.0 II N
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1-000 10 2.0 50 IC 20 50 100
VR, REVERSE VOLTAGE IVOLTS) 鈥楥. COLLECTOR CURRENT(mA(
FIGURE 4鈥?鈥淥N鈥? VOLTAGES FIGURE 5鈥擠C SAFE OPERATING AREA
OiR鈥?Tt5tt LEt
B 200
VBE@VCE=IRV
I: Tj=150掳C
SECOND BREAKDOWN LIMITED
20 BONDING WIRE LIMITED
IHEBMALLYLIMITED@TC=25掳C
OILIIrIIIIHH ill S.O1I1H[F Ti
0.2 VCEImO@ C115 10 10 鈥?5.0 10 20 50 100 20 30 413 RU 00100 200 300400
IC,COLLECTDR CURRENT)ITIAI
VCE,CDLLECTDR-EMLTTER VOLTAGE (VOLTS)

BQ4010MA-200 datasheet

Mon, 30 Apr 2012 17:15:04 -0400

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bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
8 k 8 NONVOLATILE SRAM (5 V, 3.3 V)
FEATURES GENERAL DESCRIPTION
Data Retention for at least 10 Years Without The CMOS bq4010/Y/LY is a nonvolatile 65,536-bit
Power static RAM organized as 8,192 words by 8 bits. The
Automatic Write-Protection During
Power-up/Power-down Cycles
Conventional SRAM Operation, Including
Unlimited Write Cycles
Internal Isolation of Battery before Power
Application
integral control circuitry and lithium energy source provide reliable nonvolatility coupled with the unlimited write cycles of standard SRAM.
The control circuitry constantly monitors the single supply for an out-of-tolerance condition. When VCC falls out of tolerance, the SRAM is unconditionally write-protected to prevent an inadvertent write
5-V or 3.3-V Operation operation.
Industry Standard 28-Pin DIP Pinout or At this time the integral energy source is switched on
34-Pin LIFETIME LITHIUM鈩?SMD Pinout to sustain the memory until after VCC returns valid.
Snap-on, Replaceable Lithium Battery The bq4010/Y/LY uses extremely low standby for SMD Device current CMOS SRAMs, coupled with small lithium (Device Number: bq401BATCAP) coin cells to provide nonvolatility without long
write-cycle times and the write-cycle limitations associated with EEPROM.
The bq4010/Y/LY requires no external circuitry and is compatible with the industry-standard 64-Mb SRAM pinout.
PIN CONNECTIONS
28鈭扨in DIP Module
(TOP VIEW)
34鈭扨in
Lifetime Lithium Module
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 漏 1999鈥?007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
DEVICE INFORMATION

Table 1. TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
LLM-34
VCC = 3.3 V
LLM-34
VCC = 5 V
Address inputs
Battery warning output (open drain)
Chip-enable input
Data input/output
No connect
Output enable input
Power-up reset to system CPU output (open drain)
Supply voltage input
Ground
Write enable input
2 Submit Documentation Feedback
FUNCTIONAL DESCRIPTION
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
When power is valid, the bq4010/Y/LY operates as a standard CMOS SRAM. During power-down and power-up cycles, the bq4010/Y/LY acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD. The bq4010 monitors for VPFD = 4.62 V typical for use in 5-V systems with 5% supply tolerance. The bq4010Y monitors for VPFD = 4.37 V typical for use in 5-V systems with 10% supply tolerance. The bq4010LY monitors for VPFD = 2.90 V (typ) for use in 3.3-V systems.
When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as don't care. If a valid access is in process at the time of power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time tWPT, write-protection takes place.
As VCC falls past VPFD and approaches VSO, the control circuitry switches to the internal lithium backup supply, which provides data retention until valid VCC is applied.
When VCC returns to a level above the internal backup cell voltage, the supply is switched back to VCC. After VCC
ramps above the VPFD threshold, write-protection continues for a time tCER (120 ms maximum in 5-V system,
85 ms maximum in 3.3-V system) to allow for processor stabilization. Normal memory operation may resume
after this time.
The internal coin cells used by the bq4010/Y/LY have an extremely long shelf life and provide data retention for more than 10 years in the absence of system power.
As shipped from TI, the integral lithium cells of the MT-type module are electrically isolated from the memory. (Self-discharge in this condition is approximately 0.5% per year.) Following the first application of VCC, this isolation is broken, and the lithium backup provides data retention on subsequent power-downs. The LIFETIME LITHIUM package option is shipped as two devices, which must be ordered separately.
Submit Documentation Feedback 3
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
BLOCK DIAGRAM
DIP MODULE bq4010/Y/LY MA PACKAGE
LIFETIME LITHIUM
bq4010Y/LY EBZ PACKAGE
8 k 脳 8
SRAM WE Block
A0 - A12
DQ0 - DQ7
8 k 脳 8
SRAM WE Block
A0 - A12
DQ0 - DQ7
Power CECON
Power CECON
CE Power-Fail
Control
CE Power-Fail
Control
Lithium
bq401BATCAP
+ Lithium
UDG-06075
4 Submit Documentation Feedback
bq4010/Y/LY

ORDERING INFORMATION
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
For the most current package and ordering information, see the Package Option Addendum at the end of the datasheet, or see the TI website at.
SELECTION GUIDE
DEVICE NUMBER
MAXIMUM ACCESS TIME (ns)
NEGATIVE SUPPLY TOLERANCE
NOMINAL INPUT VOLTAGE
VCC (V)
TEMPERATURE ( C)
bq4010MA-70
0 to 70
bq4010MA-85
bq4010MA-150
bq4010MA-200
bq4010YMA-70
bq4010YMA-85
bq4010YMA-150
bq4010YMA-200
bq4010YMA-70N
-40 to 85
bq4010YMA-85N
bq4010YMA-150N
bq4010YEBZ-70N
Lifetime Lithium
bq4010LYMA-70N
bq4010LYEBZ-70N
Lifetime Lithium
PART NUMBERING
PRODUCT LINE
MEMORY DENSITY
INPUT VOLTAGE (V)
NEGATIVE SUPPLY TOLERANCE
PACKAGE
SPEED (ns)
TEMPERATURE ( C)
10 = 8 k 8
11 = 32 k 8
13 = 128 k 8
14 = 256 k 8
15 = 512 k 8
16 = 1024 k 8
17 = 2048 k 8
Blank = 5
Blank = 5% Y = 10%
MA = DIP EBZ = SMD
Blank = Commercial
( 0 to 70)
N = Industrial
(-40 to 85)
Submit Documentation Feedback 5
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
ABSOLUTE MAXIMUM RATINGS (1)
PARAMETER
CONDITION
VCC DC voltage applied on VCC relative to VSS
bq4010Y
鈥?.3 to 7.0
bq4010
鈥?.3 to 7.0
bq4010LY
鈥?.3 to 6.0
VT DC voltage applied on any pin excluding
VCC relative to VSS
VVT VCC +0.3 V
bq4010Y
鈥?.3 to 7.0
bq4010
鈥?.3 to 7.0
bq4010LY
鈥?.3 to (VCC + 0.3)
TOPR Operating temperature
Commercial
0 to 70
Industrial
鈥?0 to 85
TSTG Storage temperature
Commercial
鈥?0 to 70
Industrial
鈥?0 to 85
TBIAS Temperature under bias
Commercial
鈥?0 to 70
Industrial
鈥?0 to 85
TSOLDER Soldering temperature
For 10 seconds
(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (TA = TOPR)
MIN TYP (1) MAX
VCC Supply voltage
bq4010Y
4.50 5.00 5.50
bq4010
4.75 5.00 5.50
bq4010LY
3.00 3.30 3.60
VSS Supply voltage
VIL Low-level input voltage
鈥?.3 0.8
VIH High-level Input voltage
2.2 VCC + 0.3
(1) Typical values indicate operation at TA = 25 C.
CAPACITANCE (TA = 25 C, f = 1 MHz, VCC = 5.0 V or VCC = 3.3 V)
PARAMETER (1)
TEST CONDITIONS
MIN TYP MAX
Input/output capacitance
Output voltage = 0 V
Input capacitance
Input voltage = 0 V
(1) Ensured by design. Not production tested.
DC ELECTRICAL CHARACTERISTICS
TA = TOPR, VCC(min) VCC VCC(max)
(1) Typical values indicate operation at TA = 25 C, VCC = 5.0 V or VCC = 3.3 V.
6 Submit Documentation Feedback
DC ELECTRICAL CHARACTERISTICS (continued)
TA = TOPR, VCC(min) VCC VCC(max)
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
PARAMETER
TEST CONDITIONS
MIN TYP (1) MAX
Power-fail-detect voltage
bq4010
4.55 4.62 4.75
bq4010Y
4.30 4.37 4.50
bq4010LY
2.85 2.90 2.95
Supply switch-over voltage
bq4010
bq4010Y
bq4010LY
TRUTH TABLE
I/O OPERATION
Not selected
High-Z
Standby
Output disable
High-Z
Active
Active
Active
Submit Documentation Feedback 7
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
AC TEST CONDITIONS
PARAMETER
TEST CONDITIOINS
Input pulse levels
0 V to 3.0 V
0 V to VCC
Input rise and fall times
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figure 1 and Figure 2
See Figure 3 and Figure 4
1.9 kW
Figure 1. 5-V Output Load A Figure 2. 5-V Output Load A
+ 3.3 V
+ 3.3 V
1.2 kW
Figure 3. 3.3-V Output Load B Figure 4. 3.3-V Output Load B
8 Submit Documentation Feedback
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Table 2. READ CYCLE (TA = TOPR, VCC(min) VCC VCC(max))
PARAMETER
TEST CONDITIONS
MIN MAX
MIN MAX
MIN MAX
MIN MAX
Read cycle time
Address access time
Output load A
Chip enable access time
Output enable to output valid
Chip enable to output in low Z
Output load B
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
Output load A
Address
Previous Data Valid Data Valid
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = OE = VIL.
Figure 5. Read Cycle No. 1 (Address Access) (1)(2)
tCLZ tCHZ
High鈭抁 High鈭抁
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = OE = VIL.
(3) Address is valid prior to or coincident with CE transition low.
Figure 6. Read Cycle No. 2 (CE Access) (1)(2)(3)
Submit Documentation Feedback 9
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Address
Data Valid
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = VIL.
Figure 7. Read Cycle No. 3 (OE Access) (1)(2)
10 Submit Documentation Feedback
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Table 3. WRITE CYCLE (TA = TOPR, VCC(min) VCC VCC(max))
(1) A write ends at the earlier transition of CE going high and WE going high.
(2) A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low. (3) Either tWR1 or tWR2 must be met.
(4) Ei ther tDH1 or tDH2 must be met.
(5) If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
Address
tAW tWR1
tDW tDH1
Data鈭扞n Valid
tWZ tOW
DOUT Data Undefined (1)
(1) CE or WE must be high during address transition.
(2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied.
(3) If OE is high, the I/O pins remain in a state of high impedance.
Figure 8. Write Cycle No. 1 (WE-Controlled) (1)(2)(3)
Submit Documentation Feedback 11
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Address
tDW tDH2
Data鈭抜n Valid
DOUT Data Undefined (1)
(1) CE or WE must be high during address transition.
(2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied.
(3) If OE is high, the I/O pins remain in a state of high impedance. (4) Either tWR1 or tWR2 must be met.
(5) Either tDH1 or tDH2 must be met.
Figure 9. Write Cycle No. 2 (CE-Controlled) (1)(2)(3)(4)(5)
12 Submit Documentation Feedback
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Table 4. 5-V POWER-DOWN/POWER-UP (TA = TOPR)
PARAMETER
TEST CONDITIONS
MIN TYP (1) MAX
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
VCC slew, VSO to VPFD (max.)
Chip enable recovery time
Time during which SRAM is write-protected after
VCC passes VPFD on power-up.
40 80 120
Data-retention time in absence of VCC
TA = 25 C (2)
Write-protect time
Delay after VCC slews down past VPFD before SRAM
is writeprotected.
40 100 150
(1) Typical values indicate operation at TA = 25 C, VCC = 5V.
(2) Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power
beginning when power is first applied to the device.
VPFD VPFD
VSO VSO
tFS tDR
Figure 10. 5-V Power-Down/Power-Up Timing
Submit Documentation Feedback 13
bq4010/Y/LY
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Table 5. 3.3-V POWER-DOWN/POWER-UP (TA = TOPR)
PARAMETER
TEST CONDITIONS
MIN TYP (1) MAX
VCC slew, 3 V to 0 V
VCC slew, VSO to VPFD (max)
Chip enable recovery time
Time during which SRAM is write-protected after
VCC passes VPFD on power-up.
Data-retention time in absence of VCC
TA = 25 C (2)
(1) Typical values indicate operation at TA = 25 C, VCC = 3.3 V.
(2) Batteries are disconnected from circuit until after VCC is applied for the first time. Data retention time (tDR) is the accumulated time in
absence of power beginning when power is first applied to the device.
VPFD(max)
VSO VSO
tF tCER
Figure 11. 3.3-V Power-Down/Power-Up Timing
CAUTION:
Negative undershoots below the absolute maximum rating of -0.3 V in battery-backup mode may affect data integrity.
14 Submit Documentation Feedback
PACKAGE OPTION ADDENDUM 4-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Package
Drawing
Package
Eco Plan (2)
Lead/Ball Finish
MSL Peak Temp (3)
BQ4010LYMA-70N
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010MA-150
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010MA-200
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010MA-70
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010MA-85
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-150
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-150N
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-200
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-70
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-70N
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-85
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
BQ4010YMA-85N
ACTIVE
DIP MOD ULE
Pb-Free
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM 4-May-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICALDATA
MPDI061 鈥?MAY 2001
MA (R-PDIP-T**) PLASTIC DUAL-IN-LINE
28 PINS SHOWN
4201975/A 03/01
NOTES: A. All linear dimensions are in inches (mm).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 飩?DALLAS, TEXAS 75265 1
POST OFFICE BOX 1443 飩?HOUSTON, TEXAS 77251鈥?443
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M58655P datasheet

Mon, 30 Apr 2012 12:24:47 -0400

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MC1590G datasheet

Mon, 30 Apr 2012 12:23:21 -0400

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MOTOROLA
SEMICONDUCTOR MC159OG
TECHNICAL DATA
RF/IF/AUDIO AMPLIFIER WIDEBAND AMPLIFIER WITH AGC
鈥? . . an integrated circuit featuring wide-range AGC for use in RF/
IF amplifiers and audio amplifiers over the temperature range, SILICON MONOLITHIC
鈥?5 to +125鈥機. INTEGRATED CIRCUIT
鈥?High Power Gain 鈥?50 dB Typ at 10 MHz
45 dB Typ at 60 MHz
35 dB Typ at 100 MHz PIN CONNECTIONS
鈥?Wide-Range AGC 鈥?0 dB mm, dc to 60 MHz
鈥?Low Reverse Transfer Admittance 鈥?<10 ismhoa Typ at c.鈥?鈥?6.0 to 15-Volt Operation, Single-Polarity Power Supply ir 1 cc
G SUFRX 5cC, I,,, O,ap.u
METAL PACKAGE
O,bo鈥檃o
MAXIMUM RATINGS (TA = +25掳C unless otherwise noted)
Rating Symbor Value Unit
CASE 601 o,ow,u
ADMITTANCE PARAMETERS
Power Supply Voltage VCC +18 Vdc 1CC = + 12 Vdc, TA =
Output Supply V0 +18 Vdc f = MHz
AOC Supply V2IAOCI VCC Vdc Parameter Symbol 30 60 unit
Differential Input Voltage V 5.0 Vdc Single-Ended Qi t 0.4 5$ rnwhos
Operating Temperature Range TA 鈥?5 to +125 掳C Input Admittance bti 12 鈥?.0
Storage Temperature Range Tvtg 鈥擡s to +150 掳C Single-Ended 922 0.04 0.1 mmhos
Output Admittance 022 S 5 1 S
Junction Temperature TJ +175 掳C Forwardlrnnster 2t 150 mmltns
Admittance 2i 30 鈥?05 鈥楥 (Pin ito Pin S( (Polarl
Reverse Transfer 912 鈥? 鈥攖 ymhss
Admittance鈥?012 鈥?.5 鈥?0
REPRESENTATIVE CIRCUIT SCHEMATIC
7 VCC
鈥楾he value of Reverse Transfer Admittance includes the feedback admittance of the test circuit used in
- the mwsuremenl The total Feedback capacitance
1.5k (including test circuiti is 0.025 pF and is a more practical value for design calculations than the is颅
V2)AGCI 70 ii ternal leedhack of thedesice alone. (See Figure 101
2 5k 121 k
470 470
SCATTERING PARAMERS IVCC = + 12 Vdc,
= +25鈥機, Zo = 50 III
Oufputs TA
2.0!k }
1-(E f=MHa
Parameter Symbol 30 60 unit
inputs 31.4k 45 Input
$6 Reflectisv Sii 0.90 093 鈥?鈥樷€攃i鈥?%%-鈥攊 2.8 200 200 2.0k Coefficient O 鈥?3 le C
k .0 k Output
鈥?Rellectien S22 sag o.ge 鈥?1.1 k k
5.6 g k
Coefficient g22 30 5.5 鈥楥
yoonard
Transmission 21 ie.e 14.7 鈥?ki Case Coefficient e 128 64.3 -C Substrate 4 Reveroe
Pins 4 and 8 should both be connected to circuit ground.
Transmission t2 000048 5 0002 鈥?Coefficient e12 84. 792 鈥楥
ELECTRICAL CHARACTERISTICS (V = + 12Vdc, f = 60 MHz, SW = 1.0 MHz, TA = 鈥?5CC to +125C unless otherwise noted)
AGC Rsnge
CharacteristIc FIg. Symbol Mm
24 MAGC
1 Typ Max
(V2)AGC( = 5.0 V to 7.0 VI
(V2)AGC) 5.0 V to 7.0 V. TA = 25t)
Single-Ended Power Gem
Noise Figure
(R5 optimized for best NFl
Output Stage Current
(TA = 2SC) (TA = 25t)
60 66 -
40 45 鈥?6.0 7.0
(Sum of Pins Send 61
Output Current Matching
(Magnitude of Difference of Output Currents)
Power Supply Current
(V0 = 0 VI
(V0 = 0 V. TA = 25C)
Power Consumption 112 x CC1 lvi = 0 VI
)Vt = 0 V. TA = 25CI
TA = 25CC) ITA = 2SC(
3.5 鈥?8.0
4.0 5.6 7.5
32 3A0 鈥?0.7 鈥?鈥?鈥? 20
鈥?14 17
鈥? 鈥?240
鈥?168 204
FIGURE 1 鈥?UNNEUTRALIZED POWER GAIN versus FREQUENCY (Tuned Amplifier. See Figure 241
Vsl2Vdr
FIGURE 2鈥?VOLTAGE GAIN versus FREQUENCY
(Video Amplifier. See Figure 261
St 1 1 11,1 11111
鈥? 5LtflbQ V=iZVdc
B:i15LII
t, FREOSENCY (M421
11111111 111111111 1 rinint鈥?.1鈥橧II11IL
s.r r.t it its rails
I, FPIEQfENCY (MHii
TYPICAL CHARACTERISTICS
(V2 (AGO) = 0, = 12 Vdc, TA = +25掳C unless otherwise noted)
FIGURE 3 鈥? DYNAMIC RANGE: DUTPUT VOLTAGE eersus
INPUT VOLTAGE (Video Amplifier, See Figure 26)
FIGURE 4 鈥? VOLTAGE GAIN reran FREQUENCY
(Video Amplifier, See Figure 26)
5.0 Vcc = l2Vdc
Vp3) = 0 Volts
2.0 I - 1.0MHz
0.5 jJJEL_1Okfl
TI I 鈥?)4
F J I VCCO.0Vds
gODS鈥?10
0.02 a-
0.1 0.2 05 1.0 2.0
INPU7 VS LTAGE nV RMS)
FIGURE 5鈥?VOLTAGE GAIN AND SUPPLY CURRENT versus
SUPPLY VOLTAGE IVideo Amplif ice, See Figure 26)
I 1OMHz
- 1.0k::
03 05 10 30 5.0 10 30 54 130 300
I,FREQUENCY (MHz)
FIGURE 6鈥?TYPICAL GAIN REDUCTION Venus AGC VOLTAGE
0R(A5C) 2
MC 15000
12g 4S J
-100 kI:
鈥?4ASC RAOC-5.Gkfl I
20 40 60 00 10 12
VCC, SUPPLY VOLTAGE (VOLTS)
4 5 3.0 60 00 12 15 If 21 24 20 30
VR(AGC) ASC VOLTAGE IVOC)
FIGURE 1 鈥?TYPICAL GAIN REDUCTION Verais AGC CURRENT
FIGURE 6 鈥? FIXED TUNED POWER GAIN REDUCTION
versus TEMPERATURE See Test Circuit, Figure 24)
H100< I< 100k
鈥?30 j I
+t)205颅
-40 -20 0 20 40 60 30 100 120 140 160
AOC AGC CURRENT (+6)
鈥?2 Vdo
I =60MHz
鈥?0 EAOC = 5.6 ElI
50 52 54 5.5 5.8 6.0 6.2 64 86 60 7.0
VR(ASC( ,AOL VOLTASE (VOLTS)
TYPICAL CHARACTERISTICS (continued)
FIGURE 9鈥?POWER GAIN venus SUPPLY VOLTAGE FIGURE 10鈥?REVERSE TRANSFER ADMITTANCE rasesus
Wee T.sR Circuit Figure 24) FREOUENCY (See Parameter Table, Page 1)
- - 3
I6OMHe 鈥攇o
3060 -
540 LE - H
30 -20
2,0 40 63 54 10 12 14 16 10 20 30 40 50 100 150 200
0CC POWER SUPPLY VOLTAGE (Ado) FREQUENCY lMHol
FIGURE 11鈥?NOISE FIGURE venus FREOUENCY FIGURE 12鈥?NOISE FIGURE versus SOURCE RESISTANCE
10 -r 20
Th[HH U
wtLI I I
10 14 II
鈥? t165M4z
R0 Optimized
for minimum NE
I-3OMHa
5 20 25 39 35 40 00 60 00 00 90 100
I, FREQUENCY (MEal
Iso 106 200 400 600 IOU 206 4.0k 10k
Rg. SOURCE RESISTANCE (Ohms)
FIGURE 13鈥?NOISE FIGURE versus AGC GAIN REDUCTION
- 3011Hz
35 BW=1.OM0s鈥?z Test Cimuil Has Tuned leper
0 Prourding a Source Resistance
Opsimised (or Bear Noise Figure
5.0 鈥?j 鈥?鈥?0 -20 鈥?0 -46 鈥?0 鈥?0 鈥?0 鈥攐h
GAIN REDUCTION (do)
TYPICAL CHARACTER ISTICS (continued)
FIGURE 14 鈥? SINGLE-ENDED OUTPUT ADMITTANCE
FIGURE 15鈥?SINGLE-ENDED INPUT ADMITTANCE
;L鈥? 1 V
60 05
U 鈥?20 30 40 60 00 40
I, F800IJENCY )MAa)
26 30 40 60 80 tOo
I, FREQUENCY )MRa)
FIGURE 16 鈥? HARMONIC DISTORTION oersus AGC GAIN REDUCTION FOR AM CARRIER CFor Test Circuit, See Figure 17)
40 r m-rH
o I 107MHu
Modulation ROii AM rn 10kHz
FIGURE 17 鈥?10.7 MHz AMPLIFIER
Geinz=55dB,BW=100kHz
Load at Pin5 - 20k11
Ea 鈥? Peak no Peak Envelope ut
160 rnVpp
3 36pF
5.86 2
50 ES Load
25 Modulated 107 MAt o Conini 01 Pin S
Eo-2400rnUpp/
240 rnVpp
VR(Aoc)
50 60 Source)
MC1S900 12
o It
4.002 0.002
0 10 20
GAIN REDUCTION Idol
Li = 24 Turns, No. 22 AWG Wire
on u Ti 2-44 Micro Metal
Toroid core) 124 p9
L2 = 20 Turns, No.22 AWG Wine orn a Tt2-44 Miuro Metul Toroid Cone) 100 pFl
FIGURE 18鈥?V21 FORWARD TRANSFER ADMITTANCE RECTANGULAR PORM
FIGURE 19 鈥?Y21, FORWARD TRANSFER ADMITTANCE
POLAR FORM
1)) T 240
INPUT Pin 1
OUTPU1 PinS
I60 iT21
-n -t35
I T -225t
2ii. 60
INPUT Pin 1
OUTPET PinS
, -21t <
0 20 b 50
6, FREQUENCY MAt)
to \=31s
260 20 50 10 20 5-0 tOO 200
I, FREQUENCY )MROI
TYPICAL CHARACTERISTICS (continued)
FIGURE 20鈥?ii AND 2z INPUT AND OUTPUT FIGURE 21鈥擲11 AND 22. INPUT AND OUTPUT REFLECTION COEFFICIENT REFLECTION COEFFICIENT
FIGURE 22鈥擲r, FORWARD TRANSMISSION FIGURE 23鈥?12 REVERSE TRANSMISSION COEFFICIENT (GAIN) COEFFICIENT (FEEDEACKI
MHz o.ooi
鈥? 50MHz
TYPICAL APPLICATIONS
FIGURE 24鈥?0 MHz POWER GAIN TEST CIRCUIT
FIGURE 25 鈥?PROCEDURE FOR SETUP
USING FIGURE 24
oF Shield
Tn,i J r10 02(A0C( R456(kC0)
Cd MA0C J 2.23 mV l鈥?4d6m( 5.10 0
Xe Ounpue OP I ID nO (鈥?20dm) 5.0 V 56
Li MCTSS0G
(50 u) SF 1.0 mV (鈥?20Dm) 504 5.6
FIGURE 26鈥?VIDEO AMPLIFIER
(SOic) 鈥?C2)e_2(2A颅 ,
4AGC 鈥? o
= 0.001
Op (AG C
ar SeO
LI 1 Turn,, #20 AWS Wire, 5116鈥? Sic.,
Ci,C2,C3 鈥? (i-3D) PP
441A0C( 3
MCTS0OG
SIP鈥?Lung
IS = 6 Turn,, #14 AWO Wire, 91(6鈥?Die.,
3/4鈥?Long
C4 鈥?(i-iD) 4F
04(A0C)
鈥?IO4P 2
0.001 0F
i.SiuF
FIGURE 27鈥? 30 MHz AMPLIFIER IPower GaIn = 50 dB. 6W 1.0 MHz)
0001 uP +12 -V do
FIGURE 28鈥?100 MHz MIXER
(i-3D) pF
0002uF 4
Li MC1500G to
42(AGC) 6
ML S0(0
V4 6.00
Inpur from +
Local 0u4iaror 鈥?(i-iD) 5F
(10 MHz) ioo 2 11-30) pF
鈥?Mtc鈥? di 鈥?---鈥?-t=4reiFourpo
(i-i0(pF T 3o MHz) Spiel Inpur 鈥? ,鈥? n 7 _0._u MC1580G to
(IOOMI®
1 I-IOpF
)l36(pF 2
56k 0u4
vR(ASC1 +i2Vdu
Li 12 Turn, #22 WWG Wire one Troroid Core,
0002 uP iOoH
(T31 6 Micro Meirl or Equiu)
Ti Primary = 11 Turn, #24 AWG Wire or a Tumid Cone,
(T44-6 Micro Mnra( or 6gw,)
Secondary 2 turn, #20 AWG Wire
Li = 5 Turn,,d16 AW0 Wire, 1(412,
5(6鈥?Long
LO = IS Turn,, #20 AWE Wire one Tumid
Cure, (T44-6 Micro Meral or Equio(
FIGURE 29 鈥? TWO-STAGE 50MHz IF AMPLIFIER (Power Gain 80 dB, 9W 1.5 MHz)
/ShiCld
(1-10) Pr
0002 riP
0鈥?nr n
/ S 鈥?T2
Ourprar
(50 10)
/MCS590G =鈥? (0
/ Il-ia Ii
2 鈥樎癕ClS%G
/ 6 (i-iD pF)
30pF 3/ 1
li-Id) pF
D.DO2pF _-.-. /
+i244cS 4-
I : L 鈥? ; 0.901 oF
6FC iDyll
Ti Primary Winding = IS Turn,, #22 AWO Wire, 114鈥?ID Air Corn
Seoondarg Winding 鈥?4 Turn,, #22 AWO Aim,
Coefficient of Cmuo(inq 鈥?1 5
TO Primary Winding = ID Turn,, #22 dAD Wire, 1/41040 Core
Secondary Windieg 鈥? 2 Turn,, #22 AWG Wire, Coefficient of Coupling + 1 0
TYPICAL APPLICATIONS (continued)
FIGURE 30 鈥?SPEECH COMPRESSOR
DESCRIPTION OF SPEECH COMPRESSOR
+12V OSAF
The amplifier drives the base of a PNP MPS6517 op颅
0 t01 拢
erating common-emitter with a voltage gain of approx颅
Input 15SLFF
1.0k 1-
2 tetuF
imately 20. The control Al varies the quiescent 0 point of this transistor so that varying amounts of signal ex颅 ceed the level Vr. Diode Dl rectifies the positive peaks
of 01鈥檚 output only when these peaks are greater than
Vr 7.0 Volts. The resulting output is filtered by Cx, Ax.
+ 12 V
Ax controls the charging time constsnt or attack time.
Cx is involved in both charge and discharge. R2 (the
150 kO and input resistance of the emitter-follower 02)
03 tuFT
22t 22k
controls the decay time. Making the decay long and
+12V I R2 01
Q2 MPS8517
attack short is accomplished by making Ax small and
R2 large. IA Dsrlington emitter-follower may be needed
MPSG514 I 33k
4.7k lStk 6.8k lOtk
FIGURE 31 鈥?OUTPUT VOLTAGE access INPUT VOLTAGE
t.t,_,,,,,,,,.i Li n_li
tEEFt3t0t3t
j Mt=tsk32
81=0 si
Manured Icon Itt SIr to 1
0.00 br Values xl Ank Iron
3.0 It 4.0 mt
0.01 I J II LIII
1.5 3.0 5.0 10 30 tO 100
if extremely slow decay times are required.)
The emitter-follower 02 drives the AIX Pin 2 of the MCi 590G and reduces the gain. R3 controls the slope of signal compression. The following graph (Figure 31) details performance with R3 set to 15 kIt.
TABLE 1 鈥?DISTORTION versus FREQUENCY
FREQUENCY DISTORTION DISTORTION
lOmV e lGOinVe1 tO rnVe lOOmVs1
100 Hz 3.5% 12% t5% 27%
300Hz 2% 10% 6% 20%
1.0kHz 1.5% 8% 3% 9%
10kHz 1.5% 8% 1% 3%
100kHz 1.5% 8% 1% 3% Notes 1 and 2 Notes 3 and 4
Note. Ill Decay300ns
Attack 20 tnt
21 C 7.5tuF
Ax 0 (Shorti
(31 Decay = 20 mt
Attack 3 ma
ci, INPUT VOLTAOS mV)
(41 lDt =0.6SsuF
Ax = 1.5 kIT
FIGURE 32鈥?OUTPUT CURRENT, CURRENT MATCH AND ICC FIxTURE
F 鈥榗c

LTC1334 datasheet

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Single 5V RS232/RS485
Multiprotocol Transceiver
FEATURES
鈻? Four RS232 Transceivers or Two RS485
Transceivers on One Chip
鈻? Operates from a Single 5V Supply
鈻? Withstands Repeated 飩?10kV ESD Pulses
鈻? Uses Small Charge Pump Capacitors: 0.1飦璅
鈻? Low Supply Current: 8mA Typical
鈻? 10飦瑼 Supply Current in Shutdown
鈻? Self-Testing Capability in Loopback Mode
鈻? Power-Up/Down Glitch-Free Outputs
鈻? Driver Maintains High Impedance in Three-State, Shutdown or with Power Off
鈻? Thermal Shutdown Protection
鈻? Receiver Inputs Can Withstand 飩?25V
APPLICATIO S
鈻? Low Power RS485/RS422/RS232/EIA562 Interface
鈻? Software-Selectable Multiprotocol Interface Port
鈻? Cable Repeaters
鈻? Level Translators
DESCRIPTIO
The LTC庐1334 is a low power CMOS bidirectional trans- ceiver featuring two reconfigurable interface ports. It can be configured as two RS485 differential ports, as two dual RS232 single-ended ports or as one RS485 differential port and one dual RS232 single-ended port. An onboard charge pump requires four 0.1飦璅 capacitors to generate boosted positive and negative supplies, allowing the RS232 drivers to meet the RS232 飩?V output swing requirement with only a single 5V supply. A shutdown mode reduces the ICC supply current to 10飦瑼.
The RS232 transceivers are in full compliance with RS232 specifications. The RS485 transceivers are in full compli- ance with RS485 and RS422 specifications. All interface drivers feature short-circuit and thermal shutdown pro- tection. An enable pin allows RS485 driver outputs to be forced into high impedance, which is maintained even when the outputs are forced beyond supply rails or power is off. Both driver outputs and receiver inputs feature
飩?0kV ESD protection. A loopback mode allows the driver outputs to be connected back to the receiver inputs for
diagnostic self-test.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
DR ENABLE 23
1 28 27
LTC1334
RS485 INTERFACE
27 28 1
LTC1334
DR ENABLE
4000-FT 24-GAUGE TWISTED PAIR 10
0V 8 20 5V
RS232 INTERFACE
RX OUT RX OUT
DR IN DR IN
ALL CAPACITORS: 0.1飦璅 MONOLITHIC CERAMIC TYPE
LTC1334 鈥?TA01
ABSOLUTE
(Note 1)
RATI GS
PACKAGE/ORDER I FOR ATIO
Supply Voltage (VCC) ............................................. 6.5V Input Voltage
Drivers ................................... 鈥?0.3V to (VCC + 0.3V) Receivers ............................................. 鈥?25V to 25V ON/OFF, LB, SEL1, SEL2 ........ 鈥?0.3V to (VCC + 0.3V)
Output Voltage
Drivers ................................................. 鈥?18V to 18V Receivers ............................... 鈥?0.3V to (VCC + 0.3V)
Short-Circuit Duration
Output ........................................................ Indefinite
VDD, VEE, C1+, C1鈥? C2+, C2鈥?.......................... 30 sec
Operating Temperature Range
C1+ 1
C1鈥? 2
VDD 3
SEL1 8
SEL2 9
GND 14
TOP VIEW
28 C2+
27 C2鈥?26 VCC
25 RB1
24 RA1
23 DZ1/DE1
22 DY1
20 ON/OFF
19 DY2
18 DZ2/DE2
17 RA2
16 RB2
ORDER PART
LTC1334CG LTC1334CNW LTC1334CSW LTC1334IG LTC1334ISW
Commercial ........................................... 0飩癈 to 70飩癈 Industrial ............................................ 鈥?40飩癈 to 85飩癈
G PACKAGE
28-LEAD PLASTIC SSOP
NW PACKAGE
28-LEAD PDIP WIDE
Storage Temperature Range ................ 鈥?65飩癈 to 150飩癈
SW PACKAGE
28-LEAD PLASTIC SO WIDE
Lead Temperature (Soldering, 10 sec) ................ 300飩癈
= 125飩癈, 飦盝A
= 90飩癈/ W (G)
TJMAX = 125飩癈, 飦盝A = 56飩癈/ W (NW)
TJMAX = 125飩癈, 飦盝A = 85飩癈/ W (SW)
Consult factory for Military grade parts.
DC ELECTRICAL CHARACTERISTICS
The 鈼?denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25飩癈. VCC = 5V, C1 = C2 = C3 = C4 = 0.1飦璅 (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RS485 Driver (SEL1 = SEL2 = High)
VOD1 Differential Driver Output Voltage (Unloaded) IO = 0 鈼?6 V
VOD2 Differential Driver Output Voltage (With Load) Figure 1, R = 50飦?(RS422) 鈼?2.0 6 V Figure 1, R = 27飦?(RS485) 鈼?1.5 6 V
飦刅OD Change in Magnitude of Driver Differential Figure 1, R = 27飦?or R = 50飦? 鈼?0.2 V Output Voltage for Complementary Output States
VOC Driver Common Mode Output Voltage Figure 1, R = 27飦?or R = 50飦? 鈼?3 V
飦勶偨VOC飩斤€?Change in Magnitude of Driver Common Mode Figure 1, R = 27飦?or R = 50飦? 鈼?0.2 V Output Voltage for Complementary Output States
IOSD Driver Short-Circuit Current 鈥?7V 飩?VO 飩?12V, VO = High 鈼?35 250 mA
鈥?7V 飩?VO 飩?12V, VO = Low (Note 4) 鈼?10 250 mA
IOZD Three-State Output Current (Y, Z) 鈥?7V 飩?VO 飩?12V 鈼? 飩?5 飩?500 飦瑼
RS232 Driver (SEL1 = SEL2 = Low)
VO Output Voltage Swing Figure 4, RL = 3k, Positive 鈼? 5 6.5 V Figure 4, RL = 3k, Negative 鈼? 鈥? 鈥?6.5 V
IOSD Output Short-Circuit Current VO = 0V 鈼? 飩?60 mA
Driver Inputs and Control Inputs
VIH Input High Voltage D, DE, ON/OFF, SEL1, SEL2, LB 鈼? 2 V VIL Input Low Voltage D, DE, ON/OFF, SEL1, SEL2, LB 鈼? 0.8 V
IIN Input Current D, SEL1, SEL2 鈼? 飩?10 飦瑼 DE, ON/OFF, LB 鈼? 鈥? 鈥?15 飦瑼
DC ELECTRICAL CHARACTERISTICS The 鈼?denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25飩癈. VCC = 5V, C1 = C2 = C3 = C4 = 0.1飦璅 (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RS485 Receiver (SEL1 = SEL2 = High)
VTH Differential Input Threshold Voltage 鈥?7V 飩?VCM 飩?12V, LTC1334C 鈼? 鈥?0.2 0.2 V
鈥?V 飩?VCM 飩?7V, LTC1334I 鈼? 鈥?.3 0.3 V
飦刅TH Input Hysteresis VCM = 0V 70 mV IIN Input Current (A, B) VIN = 鈥?7V 鈼? 鈥?0.8 mA
VIN = 12V 鈼? 1.0 mA
RIN Input Resistance 鈥?7V 飩?VIN 飩?12V 鈼? 12 24 k飦?RS232 Receiver (SEL1 = SEL2 = Low)
VTH Receiver Input Threshold Voltage Input Low Threshold 鈼?0.8 V Input High Threshold 鈼? 2.4 V
飦刅TH Receiver Input Hysteresis 0.6 V RIN Receiver Input Resistance VIN = 飩?10V 3 5 7 k飦?Receiver Output
VOH Receiver Output High Voltage IO = 鈥?3mA, VIN = 0V, SEL1 = SEL2 = Low 鈼? 3.5 4.6 V VOL Receiver Output Low Voltage IO = 3mA, VIN = 3V, SEL1 = SEL2 = Low 鈼? 0.2 0.4 V IOSR Short-Circuit Current 0V 飩?VO 飩?VCC 鈼? 7 85 mA IOZR Three-State Output Current ON/OFF = Low 鈼? 飩?10 飦瑼 ROB Inactive 鈥淏鈥?Output Pull-Up Resistance (Note 5) ON/OFF = High, SEL1 = SEL2 = High 50 k飦?Power Supply Generator
VDD VDD Output Voltage No Load, ON/OFF = High 8.5 V IDD = 鈥?10mA, ON/OFF = High 7.6 V
VEE VEE Output Voltage No Load, ON/OFF = High 鈥?7.7 V IEE = 10mA, ON/OFF = High 鈥?6.9 V
Power Supply
ICC VCC Supply Current No Load, SEL1 = SEL2 = High 鈼? 8 25 mA No Load Shutdown, ON/OFF = 0V 鈼? 10 100 飦瑼
AC ELECTRICAL CHARACTERISTICS
The 鈼?denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25飩癈. VCC = 5V, C1 = C2 = C3 = C4 = 0.1飦璅 (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RS232 Mode (SEL1 = SEL2 = Low)
SR Slew Rate Figure 4, RL = 3k, CL = 15pF 鈼? 30 V/飦璼
Figure 4, RL = 3k, CL = 1000pF 鈼? 4 V/飦璼
tT Transition Time Figure 4, RL = 3k, CL = 2500pF 鈼? 0.22 1.9 3.1 飦璼 tPLH Driver Input to Output Figures 4, 9, RL = 3k, CL = 15pF 鈼? 0.6 4 飦璼 tPHL Driver Input to Output Figures 4, 9, RL = 3k, CL = 15pF 鈼? 0.6 4 飦璼 tPLH Receiver Input to Output Figures 5, 10 鈼? 0.3 6 飦璼 tPHL Receiver Input to Output Figures 5, 10 鈼? 0.4 6 飦璼 RS485 Mode (SEL1 = SEL2 = High)
tPLH Driver Input to Output Figures 2, 6, RL = 54飦? CL = 100pF 鈼? 20 40 70 ns tPHL Driver Input to Output Figures 2, 6, RL = 54飦? CL = 100pF 鈼? 20 40 70 ns tSKEW Driver Output to Output Figures 2, 6, RL = 54飦? CL = 100pF 鈼? 5 15 ns tr, tf Driver Rise and Fall Time Figures 2, 6, RL = 54飦? CL = 100pF 鈼? 3 15 40 ns
AC ELECTRICAL CHARACTERISTICS
The 鈼?denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25飩癈. VCC = 5V, C1 = C2 = C3 = C4 = 0.1飦璅 (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RS485 Mode (SEL1 = SEL2 = High)
tZL Driver Enable to Output Low Figures 3, 7, CL = 100pF, S1 Closed 鈼? 50 90 ns
tZH Driver Enable to Output High Figures 3, 7, CL = 100pF, S2 Closed 鈼? 50 90 ns tLZ Driver Disable from Low Figures 3, 7, CL = 15pF, S1 Closed 鈼? 50 90 ns tHZ Driver Disable from High Figures 3, 7, CL = 15pF, S2 Closed 鈼? 60 90 ns tPLH Receiver Input to Output Figures 2, 8, RL = 54飦? CL = 100pF 鈼? 20 60 140 ns tPHL Receiver Input to Output Figures 2, 8, RL = 54飦? CL = 100pF 鈼? 20 70 140 ns
tSKEW Differential Receiver Skew, 飩絫PLH 鈥?tPHL飩? Figures 2, 8, RL = 54飦? CL = 100pF 10 ns
Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
Note 3: All typicals are given at VCC = 5V, C1 = C2 = C3 = C4 = 0.1飦璅
and TA = 25飩癈.
Note 4: Short-circuit current for RS485 driver output low state folds back above VCC. Peak current occurs around VO = 3V.
Note 5: The 鈥淏鈥?RS232 receiver output is disabled in RS485 mode (SEL1 = SEL2 = high). The unused output driver goes into a high impedance mode and has a resistor to VCC. See Applications Information section for more details.
TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Output High Voltage vs Temperature
IOUT = 3mA VCC = 5V
Receiver Output Low Voltage vs Temperature
IOUT = 3mA VCC = 5V
RS485 Receiver Skew
飩絫PLH 鈥?tPHL飩?vs Temperature
18 VCC = 5V
25 50 75
100 125
25 50 75
100 125
25 50 75
100 125
TEMPERATURE (飩癈)
TEMPERATURE (飩癈)
TEMPERATURE (飩癈)
LTC1334 鈥?TPC01
LTC1334 鈥?TPC02
LTC1334 鈥?TPC03
TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Output Current vs Output High Voltage
TA = 25飩癈 VCC = 5V
Receiver Output Current vs Output Low Voltage
TA = 25飩癈
35 VCC = 5V
RS232 Receiver Input Threshold
Voltage vs Temperature
VCC = 5V
INPUT HIGH
INPUT LOW
2.5 3.0 3.5 4.0
2.5 3.0
75 100 125
OUTPUT VOLTAGE (V)
LTC1334 鈥?TPC04
OUTPUT VOLTAGE (V)
LTC1334 鈥?TPC05
TEMPERATURE (飩癈)
LTC1334 鈥?TPC06
Charge Pump Output Voltage vs Temperature
VDD (鈥?0mA LOAD)
VDD (NO LOAD) VCC = 5V
VEE (10mA LOAD) VEE (NO LOAD)
Supply Current
vs Temperature (RS485)
VCC = 5V NO LOAD
20 SEL 1 = SEL 2 = HIGH
Supply Current
vs Temperature (RS232)
9 VCC = 5V NO LOAD
8 SEL 1 = SEL 2 = HIGH
25 50 75
100 125
25 50 75
100 125
25 50 75
100 125
TEMPERATURE (飩癈)
TEMPERATURE (飩癈)
TEMPERATURE (飩癈)
LTC1334 鈥?TPC07
RS485 Driver Differential Output
Voltage vs Temperature
RL = 54飦?VCC = 5V
LTC1334 鈥?TPC08
RS485 Driver Differential Output
Current vs Output Voltage
TA = 25飩癈
60 VCC = 5V
RS485 Driver Skew vs Temperature
VCC = 5V
LTC1334 鈥?TPC09
25 50 75
100 125
25 50 75
100 125
TEMPERATURE (飩癈)
LTC1334 鈥?TPC10
DIFFERENTIAL OUTPUT VOLTAGE (V)
LTC1334 鈥?TPC11
TEMPERATURE (飩癈)
LTC1334 鈥?TPC12
TYPICAL PERFOR A CE CHARACTERISTICS
RS485 Driver Output High Voltage vs Output Current
TA = 25飩癈 VCC = 5V
RS485 Driver Output Low Voltage vs Output Current
TA = 25飩癈 VCC = 5V
RS485 Driver Output Short-Circuit
Current vs Temperature
VCC = 5V
(VOUT = 5V)
SOURCE (VOUT = 0V)
0 1 2 3 4 5
0 1 2 3 4 5
75 100 125
OUTPUT VOLTAGE (V)
LTC1334 鈥?TPC13
OUTPUT VOLTAGE (V)
LTC1334 鈥?TPC14
TEMPERATURE (飩癈)
LTC1334 鈥?TPC15
RS232 Driver Output Voltage vs Temperature
OUTPUT HIGH
VCC = 5V RL = 3k
OUTPUT LOW
RS232 Driver Short-Circuit
Current vs Temperature
VOUT = 0V
25 VCC = 5V
20 SOURCE
10 SINK
Driver Output Leakage Current
(Disable/Shutdown) vs Temperature
VCC = 5V
25 50 75
100 125
75 100 125
25 50 75
100 125
TEMPERATURE (飩癈)
TEMPERATURE (飩癈)
TEMPERATURE (飩癈)
LTC1334 鈥?TPC16
LTC1334 鈥?TPC17
LTC1334 鈥?TPC18
PI FU CTIO S
C1+ (Pin 1): Commutating Capacitor C1 Positive Terminal. Requires 0.1飦璅 external capacitor between Pins 1 and 2.
C1鈥?(Pin 2): Commutating Capacitor C1 Negative Terminal.
VDD (Pin 3): Positive Supply Output for RS232 Drivers. Requires an external 0.1飦璅 capacitor to ground.
A1 (Pin 4): Receiver Input. B1 (Pin 5): Receiver Input. Y1 (Pin 6): Driver Output. Z1 (Pin 7): Driver Output.
SEL1 (Pin 8): Interface Mode Select Input. SEL2 (Pin 9): Interface Mode Select Input. Z2 (Pin 10): Driver Output.
Y2 (Pin 11): Driver Output. B2 (Pin 12): Receiver Input. A2 (Pin 13): Receiver Input. GND (Pin 14): Ground.
VEE (Pin 15): Negative Supply Output. Requires an exter- nal 0.1飦璅 capacitor to ground.
PI FU CTIO S
RB2 (Pin 16): Receiver Output.
RA2 (Pin 17): Receiver Output.
DZ2/DE2 (Pin 18): RS232 Driver Input in RS232 Mode. RS485 Driver Enable with internal pull-up in RS485 mode.
DY2 (Pin 19): Driver Input.
C2 鈥?(Pin 27): Commutating Capacitor C2 Negative Termi- nal. Requires 0.1飦璅 external capacitor between Pins 27 and 28.
C2+ (Pin 28): Commutating Capacitor C2 Positive Terminal.
ON/OFF (Pin 20): A high logic input enables the transceiv- ers. A low puts the device into shutdown mode and reduces ICC to 10飦瑼. This pin has an internal pull-up.
LB (Pin 21): Loopback Control Input. A low logic level enables internal loopback connections. This pin has an internal pull-up.
DY1 (Pin 22): Driver Input.
DZ1/DE1 (Pin 23): RS232 Driver Input in RS232 Mode. RS485 Driver Enable with internal pull-up in RS485 mode.
RA1 (Pin 24): Receiver Output.
RB1 (Pin 25): Receiver Output.
VCC (Pin 26): Positive Supply; 4.75V 飩?VCC 飩?5.25V
C1鈥? 2
VDD 3
SEL2 9
27 C2鈥?DZ1/DE1
21 LB
DZ2/DE2
FU CTIO TABLES
RS485 Driver Mode
INPUTS OUTPUTS ON/OFF SEL DE D CONDITIONS Z Y
1 1 1 0 No Fault 0 1
1 1 1 1 No Fault 1 0
1 1 1 X Thermal Fault Z Z
1 1 0 X X Z Z
0 1 X X X Z Z
RS232 Driver Mode
INPUTS OUTPUTS ON/OFF SEL D CONDITIONS Y, Z
1 0 0 No Fault 1
1 0 1 No Fault 0
1 0 X Thermal Fault Z
0 0 X X Z
RS485 Receiver Mode
INPUTS OUTPUTS ON/OFF SEL B 鈥?A RA RB*
1 1 < 鈥?0.2V 0 1
1 1 > 0.2V 1 1
1 1 Inputs Open 1 1
0 1 X Z Z
*See Note 5 of Electrical Characteristics table.
RS232 Receiver Mode
INPUTS OUTPUTS ON/OFF SEL A, B RA, RB
1 0 0 1
1 0 1 0
1 0 Inputs Open 1
0 0 X Z
BLOCK DIAGRA S
Interface Configuration with Loopback Disabled
PORT 1 = RS232 MODE PORT 2 = RS232 MODE
PORT 1 = RS485 MODE PORT 2 = RS232 MODE
PORT 1 = RS232 MODE PORT 2 = RS485 MODE
PORT 1 = RS485 MODE PORT 2 = RS485 MODE
27 C2 C1 2
27 C2 C1 2
27 C2 C1 2
VDD VCC
SEL1 = 0V
SEL1 = 5V
SEL1 = 0V
SEL1 = 5V
SEL2 = 0V 9
GND 14
15 VEE
SEL2 = 0V 9
GND 14
SEL2 = 5V 9
GND 14
15 VEE
SEL2 = 5V 9
GND 14
15 VEE
LTC1334 鈥?BD01
Interface Configuration with Loopback Enabled
PORT 1 = RS232 MODE PORT 2 = RS232 MODE
PORT 1 = RS485 MODE PORT 2 = RS232 MODE
PORT 1 = RS232 MODE PORT 2 = RS485 MODE
PORT 1 = RS485 MODE PORT 2 = RS485 MODE
27 C2 C1 2
27 C2 C1 2
27 C2 C1 2
VDD VCC
SEL1 = 0V
SEL2 = 0V 9
Y1 6
SEL1 = 5V
SEL2 = 0V 9
Y1 6
SEL1 = 0V
SEL2 = 5V 9
Y1 6
SEL1 = 5V
SEL2 = 5V 9
GND 14
LTC1334 鈥?BD02
TEST CIRCUITS
SEL Z D
LTC1334 鈥?F01
Figure 1. RS422/RS485
Driver Test Load
LTC1334 鈥?F02
Figure 2. RS485 Driver/Receiver
Timing Test Circuit
LTC1334 鈥?F03
Figure 3. RS485 Driver Output
Enable/Disable Timing Test Load
VIN VOUT
LTC1334 鈥?F04
LTC1334 鈥?F05
Figure 4. RS232 Driver
Swing/Timing Test Circuit
Figure 5. RS232 Receiver
Timing Test Circuit
SWITCHI G WAVEFOR S
f = 1MHz: tr 飩?10ns: tf 飩?10ns
= V(Z) 鈥?V(Y)
LTC1334 鈥?F06
Figure 6. RS485 Driver Propagation Delays
SWITCHI G WAVEFOR S
DE 1.5V
f = 1MHz: tr 飩?10ns: tf 飩?10ns
5V Y, Z
tZL tLZ
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
0.5V
LTC1334 鈥?F07
Figure 7. RS485 Driver Enable and Disable Times
f = 1MHz: tr 飩?10ns: tf 飩?10ns
tPLH tPHL
LTC1334 鈥?F08
Figure 8. RS485 Receiver Propagation Delays
1.5V 1.5V
tPHL tPLH
LTC1334 鈥?F09
Figure 9. RS232 Driver Propagation Delays
1.3V 1.7V
tPHL tPLH
LTC1334 鈥?F10
Figure 10. RS232 Receiver Propagation Delays
APPLICATI
S I FOR ATIO
Basic Theory of Operation
The LTC1334 has two interface ports. Each port may be configured as a pair of single-ended RS232 transceivers or as a differential RS485 transceiver by forcing the port鈥檚 selection input to a low or high, respectively. The LTC1334 provides two RS232 drivers and two RS232 receivers or one RS485 driver and one RS485 receiver per port. All the interface drivers feature three-state outputs. Interface outputs are forced into high imped- ance when the driver is disabled, in the shutdown mode or with the power off.
All the interface driver outputs are fault-protected by a current limiting and thermal shutdown circuit. The ther- mal shutdown circuit disables both the RS232 and RS485 driver outputs when the die temperature reaches 150飩癈. The thermal shutdown circuit reenables the drivers when the die temperature cools to 130飩癈.
In RS485 mode, shutdown mode or with the power off, the input resistance of the receiver is 24k. The input resistance drops to 5k in RS232 mode.
A logic low at the ON/OFF pin shuts down the device and forces all the outputs into a high impedance state. A logic high enables the device. An internal 4飦瑼 current source to VCC pulls the ON/OFF pin high if it is left open.
In RS485 mode, an internal 4飦瑼 current source pulls the driver enable pin high if left open. The RS485 receiver has a 4飦瑼 current source at the noninverting input. If both the RS485 receiver inputs are open, the output goes to a high state. Both the current sources are disabled in the RS232 mode. The receiver output B is inactive in RS485 mode and has a 50k pull-up resistor to provide a known output state in this mode.
A loopback mode enables internal connections from driver outputs to receiver inputs for self-test when the LB pin has a low logic state. The driver outputs are not isolated from the external loads. This allows transmitter verification under the loaded condition. An internal 4飦瑼 current source pulls the LB pin high if left open and disables the loopback configuration.
RS232/RS485 Applications
The LTC1334 can support both RS232 and RS485 levels with a single 5V supply as shown in Figure 11.
Multiprotocol Applications
The LTC1334 is well-suited for software controlled inter- face mode selection. Each port has a selection pin as shown in Figure 12. The single-ended transceivers sup- port both RS232 and EIA562 levels. The differential trans- ceivers support both RS485 and RS422.
0.1飦璅 2
LTC1334
27 0.1飦璅
RS485 I/O 120飦?DR ENABLE
飩?飩?V INTO
3k飦? LOAD
RS232 DR OUT 11
RS232 DR OUT 10
RS232 RX IN 13
RS232 RX IN
19 DR IN
16 RX OUT
LTC1334 鈥?F11
Figure 11. RS232/RS485 Interfaces
APPLICATI
0.1飦璅 2
I FOR ATIO
LTC1334 28
27 0.1飦璅 C2
Each receiver in the LTC1334 is designed to present one unit load (5k飦?nominal for RS232 and 12k飦?minimum for
INTERFACE
INPUT A K1A
INPUT B
OUTPUT A K1B
0.1飦璅 RX OUT
RX OUT DR IN
RS485) to the cable. Some RS485 and RS422 applications
call for terminations, but these are only necessary at two nodes in the system and they must be disconnected when operating in the RS232 mode. A relay is the simplest, low- est cost method of switching terminations. In Figure 12
TERM1 and TERM2 select 120飦?terminations as needed. If terminations are needed in all RS485/RS422 applica-
tions, no extra control signals are required; simply con- nect TERM1 and TERM2 to SEL1 and SEL2.
TX2A-5V
OUTPUT B
DR IN/ENABLE
Typical Applications
FMMT619**
20 ON/OFF
A typical RS232/EIA562 interface application is shown in
Figure 13 with the LTC1334.
INTERFACE
TX2A-5V
INPUT A
INPUT B
OUTPUT A
OUTPUT B
RX OUT
DR IN/ENABLE
A typical connection for a RS485 transceiver is shown in Figure 14. A twisted pair of wires connects up to 32 drivers and receivers for half duplex multipoint data transmission. The wires must be terminated at both ends with resistors equal to the wire鈥檚 characteristic impedance. An optional shield around the twisted pair helps to reduce unwanted noise and should be connected to ground at only one end.
1/2 LTC1334 1/2 LTC1334
FMMT619**
*AROMAT CORP (800) 276-6289
**ZETEX (516) 543-7100
LTC1334 鈥?F12
11 RS232/ 4
10 EIA562 5
13 INTERFACE 6
12 LINES 7
24 RX OUT
25 RX OUT
22 DR IN
23 DR IN
Figure 12. Multiprotocol Interface
with Optional, Switchable Terminations
LTC1334 鈥?F13
Figure 13. Typical Connection for RS232/EIA562 Interface
1/2 LTC1334
1/2 LTC1334
DR ENABLE
7 6 5 4
18 DR ENABLE
19 DR IN
LTC1334
22 23 24 8
DR IN RX OUT
DR ENABLE 5V
Figure 14. Typical Connection for RS485 Interface
LTC1334 F14
APPLICATI
S I FOR ATIO
A typical RS422 connection (Figure 15) allows one driver and ten receivers on a twisted pair of wires terminated with a 100飦?resistor at one end.
A typical twisted-pair line repeater is shown in Figure 16. As data transmission rate drops with increased cable length, repeaters can be inserted to improve transmission rate or to transmit beyond the RS422 4000-foot limit.
The LTC1334 can be used to translate RS232 to RS422 interface levels or vice versa as shown in Figure 17. One
port is configured as an RS232 transceiver and the other as an RS485 transceiver.
Using two LTC1334s as level translators, the RS232/ EIA562 interface distance can be extended to 4000 feet with twisted-pair wires (Figure 18).
AppleTalk庐/LocalTalk庐 Applications
Two AppleTalk applications are shown in Figure 19 and 20 with the LTC1323 and the LTC1334.
AppleTalk and LocalTalk are registered trademarks of Apple Computer, Inc.
1/2 LTC1334
DR ENABLE
1/2 LTC1334
1/2 LTC1334
DR IN 22
18 DR ENABLE
RX OUT 24
LTC1334 鈥?F15
Figure 15. Typical Connection for RS422 Interface
5V RX IN 13
17 22
24 22
RS232/EIA562
LTC1334
LTC1334 鈥?F17
1/2 LTC1334
LTC1334 鈥?F16
9 19 24
Figure 16. Typical Cable Repeater for RS422 Interface
Figure 17. Typical RS232/EIA562 to RS422 Level Translator
17 22
24 19
RS232/EIA562
LTC1334
LTC1334
RS232/EIA562
9 19 24
8 23
22 17 9
LTC1334 鈥?F18
Figure 18. Typical Cable Extension for RS232/EIA562 Interface
APPLICATI
S I FOR ATIO
LTC1323CS-16
2 LTC1334
27 0.1飦璅
0.33飦璅 2
CHARGE
PUMP 15
TXDEN 4
14 0.33飦璅
EMI 4
12 TXD 鈥?11 TXD +
RXDO 7
10 RXD 鈥?SEL1, 5V
21 5V
8 9 RXD +
FERRITE BEAD
FERRITE BEAD
SEL2, 5V 9
NC 10
EMI = OR OR
100pF 100pF
NC 12
16 NC
Figure 19. AppleTalk/LocalTalk Implemented Using the LTC1323CS-16 and LTC1334 Transceivers
LTC1334 鈥?F19
FERRITE BEAD
FERRITE BEAD
0.33飦璅 2
LTC1323CS
CHARGE PUMP
EMI = OR OR
100pF 100pF
2 LTC1334
27 0.1飦璅
TXD 4
22 0.33飦璅
1飦璅 3 26 5V
21 0.1飦璅
20 TXD 鈥?19 TXD +
EMI 4
RXEN 8
18 TXO
6 23 DE1
RXO 9
RXO 10
RXDO 11
17 RXI
15 RXD鈥?14 RXD+
EMI EMI
EMI 7
SEL1 8
5V 9
21 5V
EMI EMI
16 NC
LTC1334 鈥?F20
Figure 20. AppleTalk Direct Connect Using the LTC1323 DTE and the LTC1334 for DCE Transceivers
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 鈥?10.33* (0.397 鈥?0.407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 鈥?7.90 (0.301 鈥?0.311)
5.20 鈥?5.38** (0.205 鈥?0.212)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.73 鈥?1.99
(0.068 鈥?0.078)
0飩?鈥?8飩? 0.13 鈥?0.22 (0.005 鈥?0.009)
0.55 鈥?0.95 (0.022 鈥?0.037)
0.65 (0.0256) BSC
0.25 鈥?0.38
0.05 鈥?0.21 (0.002 鈥?0.008)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
(0.010 鈥?0.015)
G28 SSOP 1098
NW Package
28-Lead PDIP (Wide 0.600)
(LTC DWG # 05-08-1520)
1.455* (36.957) MAX
28 27 26 25
20 19 18
17 16 15
0.505 鈥?0.560* (12.827 鈥?14.224)
1 2 3 4 5 6 7 8 9 10
11 12 13 14
0.600 鈥?0.625 (15.240 鈥?15.875)
0.150 飩?0.005 (3.810 飩?0.127)
0.045 鈥?0.065 (1.143 鈥?1.651)
0.009 鈥?0.015 (0.229 鈥?0.381)
0.625 鈥?.015
15.87 鈥?.381
0.015 (0.381)
0.125 (3.175)
0.035 鈥?0.080 (0.889 鈥?2.032)
0.018 飩?0.003 (0.457 飩?0.076)
0.070 (1.778)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
(2.54) BSC
N28 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1690)
0.697 鈥?0.712* (17.70 鈥?18.08)
28 27 26 25
24 23
22 21 20 19 18 17 16 15
0.394 鈥?0.419 (10.007 鈥?10.643)
0.291 鈥?0.299** (7.391 鈥?7.595)
0.010 鈥?0.029 飩?45飩?(0.254 鈥?0.737)
1 2 3 4 5 6 7 8
0.093 鈥?0.104 (2.362 鈥?2.642)
9 10
11 12 13
0.037 鈥?0.045 (0.940 鈥?1.143)
0飩?鈥?8飩?TYP
0.009 鈥?0.013 (0.229 鈥?0.330)
0.016 鈥?0.050
0.050 (1.270) BSC
0.014 鈥?0.019
0.004 鈥?0.012 (0.102 鈥?0.305)
(0.406 鈥?1.270)
(0.356 鈥?0.482)
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
S28 (WIDE) 1098
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC485 Low Power RS485 Interface Transceiver Single 5V Supply, Wide Common Mode Range
LT 庐 1137A Low Power RS232 Transceiver 飩?5kV IEC-1000-4-2 ESD Protection, Three Drivers, Five Receivers
LTC1320 AppleTalk Transceiver AppleTalk/Local Talk Compliant LTC1321/LTC1322/LTC1335 RS232/EIA562/RS485 Transceivers Configurable, 10kV ESD Protection LTC1323 Single 5V AppleTalk Transceiver LocalTalk/AppleTalk Compliant 10kV ESD
LTC1347 5V Low Power RS232 Transceiver Three Drivers/Five Receivers, Five Receivers Alive in Shutdown
LTC1387 Single 5V RS232/RS485 Transceiver Single Port, Configurable, 10kV ESD
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
1334fa LT/TP 1099 2K REV A 鈥?PRINTED IN USA
(408)432-1900 鈼?FAX: (408) 434-0507
鈼?飪?LINEAR TECHNOLOGY CORPORATION 1995

LH1502 datasheet

Mon, 30 Apr 2012 02:39:34 -0400

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LH1502 / LH1502A
HIGH VOLTAGE, PHOTO MOS RELAY
65 Shark River Road, Neptune, New Jersey 07753-7423
Tel: 732-922-6333 Fax: 732-922-6363 E-Mail:
65 Shark River Road, Neptune, New Jersey 07753-7423
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LF156 datasheet

Sun, 29 Apr 2012 18:02:08 -0400

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F- U) (N
National
Semiconductor
LF1 55/LF156/LF1 57 Series Monolithic
JFET Input Operational Amplifiers
LF1 55/LF1 55A/LF255/LF355/LFS55A/ LF355B Low Supply Current
LF1 56/LF1 56A/LF256/LF356/LF356A/ LF356B Wide Band
-) LF157/LF157A/LF257/LF357/LF357A/
LL LF357B Wide Band Decompensated (AVMIN =5)
-J General Description
Co U-颅 I
These are the first monolithic JFET input operational ampli颅 fiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FETTM Tech颅 nology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common- mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low volt颅 age and current noise and a low 1 If noise corner.
Advantages
鈥?Replace expensive hybrid and module FET op amps
鈥?Rugged JFETs allow blow-out free handling compared with MOSFET input devices
鈥?Excellent for low noise applications using either high or
鈥?Photocell amplifiers
鈥?Sample and Hold circuits
Common Features
(LF1S5A, LF156A, LF157A)
鈥?Low input bias current
鈥?Low Input Offset Current
鈥?High input impedance
鈥?Low input offset voltage
鈥?Low input offset voltage temp. drift
鈥?Low input noise current
鈥?High common-mode rejection ratio
鈥?Large dc voltage gain
101 2fl
1 my
3 p.V/掳C
0.01 pA/si
low source impedance鈥攙ery low 1/f corner
鈥?Onset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers
鈥?New output stage allows use of large capacitive loads
(10,000 pF) without stability problems
鈥?Internal compensation and large differential input volt颅
age capability
Uncommon
鈥?Extremely fast settling
time to
Fast slew
Features
L.F155A LF1S6A
(Av 5) Units
Applications
鈥?Precision high speed integrators
鈥?Fast D/A and AID converters
鈥?High impedance buffers
鈥?rate
鈥?Wide gain bandwidth
Low input
5 12 50 VIgs
2.5 5 20 MHz
Co 鈥?Wideband, low noise, low drift amplifiers
-J 鈥? Logarithmic amplifiers
(N Simplified Schematic
4 BALANCE U) )l) U) I-.)
鈥?noise voltage 20 12 12 nV/4H
ID pF JC1
25 OUT
+ 鈥榩 4 SB
3 pF in ..F157 series.
U 4 eo鈥擵EE TL/H/5646鈥?1
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for 2!
availability and specifIcations.
(Note 8) (Ji
LF3558/6B/70 LF355/8/7
LF255/6/7 LF3SSA/SA/7A r
Supply Voltage 卤 22V 卤 22V 卤 22V 卤1 8V
Differential Input Voltage 卤 40V 卤 40V 卤 40V 卤 30V Ca
Input Voltage Range (Note 2) 卤 20V 卤 20V 卤 20V 卤 1 6V
Output Short Circuit Duration Continuous Continuous Continuous Continuous ci
TJMAX Cii
H-Package 150掳C 150掳C 115掳C 115掳C
N-Package 100掳C 100掳C Cii
J-Package 150掳C 115掳C 115掳C M-Package 100掳C 100掳C
Power Dissipation at TA = 25掳C (Notes 1 and 9)
H-Package (Still Air) 560 mW 560 mW 400 mW 400 mW
H-Package (400 LF/Min Air Flow) 1200 mW 1200 mW 1000 mW 1000 mW
N-Package 670 mW 670 mW
J-Package 1260 mW 900 mW 900 mW M-Package 380 mW 380 mW
Thermal Resistance (Typical) 0JA
H-Package (Still Air) 1 60掳C/W 1 60鈥機/W 1 60掳C/W 1 60掳C/W
H-Package (400 LF/Min Air Flow) 65掳C/W 65掳C/W 65掳C/W 65掳C/W N-Package 1 30掳C/W 1 30掳C/W
J-Package 1 00掳C/W 1 00掳C/W 1 00掳C/W -n
M-Package 195掳C/W 195掳C/W
(Typical) 0jc
H-Package 23掳C/W 23掳C/W 23掳C/W 23掳C/W r
StorageTemperatureRange 鈥?5掳Cto +150掳C 鈥?5掳Cto +150掳C 鈥?5掳Cto +150掳C 鈥?5掳Cto +150掳C Soldering information (Lead Temp.)
Metal Can Package
Soldering (10 sec.) 300掳C 300掳C 300掳C 300掳C
Dual-In-Line Package CIT Soldering (10 sec.) 260掳C 260掳C 260掳C
Small Outline Package
Vapor Phase (60 sec.) 215掳C 215掳C
Infrared (15 sec.) 220掳C 220掳C See AN-450 鈥淪urface Mounting Methods and Their Effect on Product Reliability鈥?for other methods of soldering surface
mount devices. r
ESD tolerance
(100 pF discharged through 1.5kfl) 1200V 1200V 1200V 1200V
DC Electrical Characteristics (Note 3) TA = T1= 25掳C
Symbol Parameter Conditions LF155A/6A/7A LF355A/OA/7A Units
Mm Typ Max Mm Typ j Max -n
V05 lnputOffsetVoltage Rs=50fl,TA=25掳C 1 2 1 2 mV Over Temperature 2.5 2.3 mV
VOS/AT AverageTCof Input Rs=50fl 3 5 3 5 V/掳C
Offset Voltage 掳鈥?TC/LV05 Change in AverageTC RS= SOft, (Note 4) 05 05 V/掳C
with Vos Adjust per mV
tmos Input Offset Current T1=25掳C, (Notes 3,5) 3 10 3 10 pA
TjEITHIGH 10 1 nA 鈥?
Lnput Bias Current Tj = 25掳C, (Notes 3, 5) 30 50 30 50 pA 2j
TjEITHIGH 25 5 nA
RIN lnputResistance T1=25掳C 1012 1012 II AVOL Large Signal Voltage Vs = 卤 1 5V, TA = 25掳C 50 200 50 200 V/mV
Gain V0=卤1OV,R1=2k 25 25 V/mV Over temperature
V0 Output VoltageSwing Vs= 卤15V, RL=IOk 卤12 卤13 卤12 卤13 V Vs=卤1SV,RL=2k 卤10 卤12 卤10 卤12 V
Co DC Electrical Characteristics (NoteS) TA = Tj = 25掳C (Continued)
l LF155A/6A/7A I
,- Symbol Parameter Conditions
Typ j Max Mm j Typ Max
Vj input Common-Mode +15.1 +15.1 V
Voltage Range
CMRR Common-Mode Rejection 85 100 85 100 dB
SRR Supply Voltage Rejection (Note 6) 85 100 85 100 dB
AC Electrical Character istics TA = Tj = 25掳C,Vs 卤1SV
LFI55A/355A LF156A/356A I LF157A/357A
Symbol Parameter
SR Slew Rate
Cenditlons I
Mm Typ Max Mm Typ f Max Mm j Typ j Max
F1S5A/6A;Av1, 3 5 10 12
LF157A;Av=5 40 50
Gain Bandwidth 2.5 4 4.5 15 20
Product
SettlingTimetoo.01% 1 (Note7) I 1 I I 1.5 1.5
Equivalent Input Noise
Co Voltage 1=100Hz 25 15 15
UI 1=1000Hz 25 12 12 nVJ
i Equivalent Input f= 100 Hz 0.01 0.01 0.01 pA/4i in Noise Current f= 1000 Hz 0.01 0.01 0.01 pA/4Fi
鈥? input Capacitance
I HI I 1I HI NE
UD颅 C Electrical Characteristics (Note 3)
LF15516/7
LF255/6/7
LF355/6/7
4 Symbol
Parameter Conditions
LF355B/68/7B
Minj Typ iMaxi Mini Typ IMaxJ Mint
Typ IMaxi
CD lnputOffsetVoltage
Rs=50fl,TA=25掳C 3 5 3 5 3 10 mV
OverTemperature 7 6.5 13 mV
4 in in Co
VrjMT AverageTCof input Rs=5011 5 5 5
Offset Voltage
ATC/AV05 Change inAverage TC Rs= son, (Note 4) 0.5 0.5 0.5
with V Adjust per mV
los Input Onset Current Tj = 25掳C, (Notes 3, 5) 3 20 3 20 3 50 pA
TjEITHIGH 20 1 2 nA
lB input Bias Current Tj =
25掳C, (Notes 3, 5) 30 100
30 100 30 200 pA
TiITHIGH 50 5 8 nA Input Resistance 1Tr25掳C 1012 1 I 1012 1012 n
ASJ Large Signal Voltage V5= 卤15V,TA=25掳C 50 200 50 200 25 200 V/mV
Gain Vo=卤1OV,RL=2k
OverTemperature 25 25 15 V/mV
t, V0 OutputVoltageSwing Vs= 卤15V, RL=lOk 卤12 卤13 卤12 卤13 卤12 卤13 V
1 Vs=卤15V,RL=2k 卤10 卤12 卤10 卤12 卤10 卤12 V
VCM Input Common-Mode V
V5=卤15V 卤11 卤11 卤_1 +10
r Voltage Range
Uj CMRR Common-Mode Rejec颅 85 100 85 100 80 100 dB
颅 tion Ratio
PSRR Supply Voltage Rejec- (Note 6) 85 100 85 100 80 100 dB
tion Ratio
DC Electrical Characteristics TA = Tj = 25掳C, Vs = 卤 1 5V
LF155A/155, LF15SA!156 L.F157A1157
LF355 LF256/356B LF3S6A/356 LF257!3578 LF3S7A/357 Units
Parameter LF355A/355B
Typ Max Typ Max Typ Max Typ Max 1 Typ Max Typ Max
SupplyCurrent 2 4 2 4 5 7 5 i0 5 7 5 10 mA 31
AC Electrical Characteristics TA = lj = 25掳C, Vs = 卤15V
LF155/255/ LF156/256, LF1S6/256/ LF157/257, LF1571257/
Symbol Parameter Conditions 355/3558 LF3568 356/3568 LF3578 357/357B Units
Typ Mm Typ Mm Typ
SR SlewRate LF155/6:Av=1, 5 7.5 12 Vps 5
LF157:Av=5 30 50 V/gs 31
GBW Gain Bandwidth 2.5 5 20 MHz 0
Product
t8 Settiing Time to 0.01% (Note 7) 4 1.5 1.5 s
en Equivaient input Noise Rs= 1008 a)
Voltage f=lOOHz 25 15 15 nViJFi
f=l000Hz 20 12 12 nV/4F 31
Equivaient Input t= 100 Hz 0.01 0.01 0.01 pA/4F
Current Noise f= 1000 Hz 0.01 0.01 0.01 pA/4Fi r
CIN Input Capacitance 3 3 3 pF
Notes for Electrical Characteristics
Note 1: The maximum power dissipation for these devices must be dereted at elevated temperatures and is dictated by TiMaiC. Op, and the ambient temperature,
TA. The maximum available power dissipation at any temperature is t鈥檇 = (TIMAX 鈥擳pj/ 9IA or the 25掳c dMAx. whichever is less. a)
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: Unless otherwise stated, these test conditions apply:
LF155A/6A/7A LF2551/6/7 LF355A/6A/7A LF355B/6B/78 LF355//6/7 >
LF1S5//6/7 C.)
SuppiyVoitage,V5 卤15VEIV5EI卤20V 卤15VEIVsEI卤20V 卤1SVEIV5EI卤18V 卤15VEIV5卤20V V5卤15V 31
TA 鈥?5掳CEITAEI+125掳C 鈥?5掳CEITAEI+85掳C 0掳CEITAEI+70掳C 0掳CEITAEI+70掳C 0掳CEITAEI+70掳C
THIGH +125掳C +85掳C +70掳C +70掳C +70掳C
and V05, l and 1os are measured at Vq=0.
Note 4: The Temperature coefficient of the adjusted input offset voltage changes only a small amount (0.Sp.V/掳c typically) for each my of adlustment trom its 鈥?J
original unad(usted vatue. lDommon-rnode rejection and open loop voltage gain are also unaffected by offset adiustment.
NoteS: The input bias currents are junction leakage currents which approximately double for every 0掳C increasa in the junction temperature, Tj. Due to limited Cii production test time, the input bias currents measured are correlated to junction temperature. In normal operation the lunction temperature rises above the ambient
temperature as a result of internal power dissipation, Pd. Ti=TA+OjA Pd where 01A is the thermal resistance from Junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. r
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing sirriultarleously, in accordance with common practice. Note 7: Settling time is defined here, for a unity gain invertar connection using 2 ku resistors Icr the LF155/S. It is the time required for the error voltage (the
voltage at tha inverting input pin on the amplifier) to settle to wIthin 0.01% of Its final value from tha time a WV step input is applied to the inverter. For the LF1 57, %t.
= 鈥?, tha feedback resistor from output to input is 2 kG and the output step is I DV (See Settling Time Test circuit).
Note B: Refer to RETSIS5AX for t.F155A, RETS1S5X for LF155, RETSF156AX for LFI5GA, RETSI56X for LF156, RETS1S1A for LF157A and RETS157X for Cr) LF157 military specifications.
Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the pert to operate outside guaranteed limits.
Cr) Cii
Typical DC Performance Characteristics
Curves are for LFI 55, LF1 56 and LF1 57 unless otherwise specified.
1掳- lb Co
input Biaa Current
Input Bias Current
input Bias Current
V0. thy
71 T*.orc
LI Ill
鈥業I V5
[jtsvS -
= 45
LFINLI
鈥?(1*11
a!,. 鈥榣ATh
25 _鈥榬
鈥?1 I 20 55 55 III
鈥?5 鈥?0 I 31 IS Ii 125
CVII lIlly hIA
4 5 5 II
C Lb Co
CASE TEIWIRATUIE rd
Voltage Swing
S IL.Zk
a TA-arc
CASE TEISRATURE (鈥楥I
Suppiy Current
Y. 鈥攕rc
COOI.NOO5 VOLTAGE (VI
Suppiy Current
鈥? Tc鈥橺S掳C
I II II 20
N Tc.llrc
LP1ISI7
C Sb N LI.
SUPPLY VOLTAGE I卤VI
Negative Current Limit
鈥擵5鈥ISV
I I 15 II 25 21
SUPPLY VOLTASE ItY)
Positive Current Limit
V5鈥?卤IIV
2 I I
鈥? I II II 20 25
SUPPLY VOLTAGE (卤VJ
Positive Common-Mode input Voitage Limit
20 I I I
鈥?0鈥機 EITAEI121掳C
Lb Lb Co
4 lb Lb Co
lb Lb Co LI.
鈥擨 I2IC
I I IS II 20 25 35 31
OUTPUT SINK CIORAENT (mA)
Negative Common-Mode
Input Voitage Limit
-2G[ 14
5 1 10 11 20 05 31 31 40
OUTPUT SOURCE CURRENT (a,A)
Open Loop Voitage Gain
0 II II 20
POSITIVE SUPPLY VOLTS (V
TL/H/56.46鈥?
Output Voitage Swing
V5 . 卤1EV
Lb Lb C1
鈥攕 TA- 鈥擲rc T-2I掳C TA. 121掳C
TA-鈥擟rc
TA 2S鈥機 TA - 121掳C
24 TA-2rc
0 II
-j 鈥擲鈥?0 鈥?5 鈥?0
NEGATIVE SUPPLY VOLTS (VI
5 10 IS
SUPPLY VOLTACE I卤V)
20 0 1.0 10
OUTPUT LOAO R1 (bfl4
TL/H/5648鈥?
Typical AC Performance Characteristics
Gain Bandwidth
Gain Bandwidth Normalized Slew Rate
1F151 CURVES IQENTICOL
I I I
16 IVp卤15V
= ak颅
BUTMULTIPLIED 0Y4
I I I I
=B v5鈥⒙眎ov 鈥?II
鈥? F%)
I vs-卤isv
O LF156
l.a LF155
i I V卤20V
0.I U鈥?卤10v ::
Cs) UI U鈥?鈥?5 鈥?6 鈥?5 5 25 45 65 05 105 125
TEMPERATURE (C(
鈥?5 鈥?5 鈥?5 5 25 45 65 05 105 125 鈥?5 鈥?5 鈥?5 5 25 45 65 05 105 125 UI TEMPERATURE (*CI TEMPERATURE (0
Output Impedance
Output Impedance
TA25C Av鈥?00
Output Impedance
TL./H/5646鈥?
C.) U鈥?vn
106 r>,11
VS- 卤ISV
V5 卤15W
a io
1 Av10 a a)
I= 01
LF15I t
15 Ilk 110k IM 100
FREQUENCY 1Hz)
LF155 Small Signal Pulse
Response, Av + I
TIME (D.5IDIV)
TL/H/5646鈥?
LF155 Large Signal Pulse
Response, Av = +1
1k 10k lOOk 1M 1GM
FREQUENCY (Hz)
LF156 Small Signal Pulse
Response, Av= + 1
TIME (05 a!DIV)
TLJH5846鈥?
LF156 Large Signal Pulse
Response, Av = +1
1k 10k 106k 7M 1GM
FREQUENCY (It.)
TL)H/5646鈥?2
Small Signal Pulse
Response, Av = + 5
TIME (0.1 ,ss/DIV(
TL/H/5646鈥?
LF157 Large Signal Pulse
Response, Ar +5
C.) CII
TIME (I s!DIV) TIME (1 .a/DIV) TIME (0.5 1a/tIV)
TL/H/5646鈥?
TL/H/5646-9
TL/H/5646鈥攍C
tg T鈥?ypical AC Performance Characteristics (Continued)
1鈥欌€?Open Loop Frequency
In lnverter Settling Time Inverter Settling Time Response
I. LFISI
II I91 iiilitr
IS) 1-arc L 鈥?V5鈥⒙盜IV I V1-tISV
1GeV 1eV
TA25掳C 50 a
1ev lI{lI
Il LFIST
In C, 0
I I LFIII.Av鈥擨 (Sill
lb 1I LFlS7.Avsl K
4 1Gev 1eV
= 0 II II
IGV 1ev I.
I 0.511 III LI I II iIiNltlbinl枚lItI
Lb SETTLING TINE (ii) SETTLING TIME Cia) FREQUENCY (Hi)
Bode Plot Bode Plot Bode Plot
IN liii 1 III IN II ItS
4 5 PHAGS LFIK II LFIIN 鈥 IN 31
Lb GAIN V卤tSV... II
MIH_!鈥? V1卤IIV .-_ 20 AU
i I . GAIN
IL 4 25 Al
l _鈥? 鈥!.I.
-II -is
鈥?-is LI
IL C-il
-N C II -N I
-20 Iil7it
鈥擨S Ill 鈥擨N 鈥擨N
鈥?0 鈥?21 鈥擨I
Cu I I 11111 鈥?21 1 1 1111111 鈥擨II 鈥攖 I I 1111111
IL I ii IN I IN IN 1 IN
FREQUENCY (MHZ) FREQUENCY (MHz) FREQUENCY MHz)
Ratio Power Supply Relectlon Ratio Power Supply Rejection Ratio
r IN 鈥?I 1 a iN a Ill I TAWC
v5-tISV
_I 0 r*-zrC IN 1
. F N RL2t C a
V5卤INV
鈥?POSITIVISUPPLY
LI) 2 I
SUPPLY N NLFINI7
5鈥? I LFIKIS I
4 4. LFIS7 NEGATIVE
SUPPLY
co 2 fl =e
NEGATIVESUPPLY X
I . 鈥楽 . III
IL lOIN It IS1NtIMIW 11 IN lb Ilk I IN IN lb IN INS IN 1W
-J FREQUENCY (Hz) FREQUENCY (HZ) FREQUENCY (Hz)
LI) LI)
Undistorted Output Voltage Equlvaient input Noise Equivalent Input Noise
4 Swing Voltage Voltage (Expanded Scale)
141 T*25掳C
TA 鈥?WE
t 24 V5鈥ISV V iI5V V5-卤1SV RL2t Iii ; N
IS) 5 21 T*aWC
鈥?Fl An
鈥? IN
It lb 5 > 12 LFI
鈥? LFISI 鈥?鈥?AyS 40 LFISW7
I S N 4 5
lob iNS IN IS I II IN lb 1Gb II lb
FREOUENCY (HZ) FREQUENCY (HZ) FREQUENCY (II
Detailed Schematic Ui
-a v CII In Ui
CII CII
CU 鈥擨II
.3 鈥業
a 03 Ui
II_鈥?CI Ii
V%脴00Ta
4. 鈥? Ui
c 4 3鈥?a I
III Ill II
C=3pFinLFl57oedee.
Connection Diagrams Jop Views)
TL/H15646-13 r
Metal Can Package (H) Dual-In-Une Package (J) Dual-In-Une Package (M and N)
NALANCII
NC IALANCC 鈥榝l
NC 2 13NC
INPUT 31 I OUTPUT BALANCE 3 12
INPUT 3 1 IALANCE
INPUT +
Ia owu
r 6 BALANCE r
NALANCE 鈥榝l
TL/H15546鈥?4
NC 7 6 NC
Order Number TL/H/5646-20
LFI55AH, LF156AH, LFIS7AH,
TLIHISC4S-30 Order Number r- I
LF155H, LF156H, LF1S2鈥橦, LF355M, LF$SSM, LF357M, LF255H, LF256H, LF257H, LF155J, LF1S6J, LFI5TJ, 11356GM, LF35SBN, LF356BN,
L.F355AH, LF35eAH, LF357AH, LF355J, LF356J, LF357J, LF357BN, LF355N, LF356N or
LF3558H, LF356BH, LF357BH, LF3555J, LF3S6GJ or LF357BJ LF357N
LF355H, LF356H or LF35TH see ris Package Number J14A See NS Package Number
See NS Package Number HOSC MO8A or NO8E
F.颅 to Cl Ii-
0 (0 to Co
4(0 to Co
(0 to CO U-
(0 to C鈥?IL
Application Hints
The LF155/6/7 series are op amps with JFET input de颅 vices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accomodated without a large in颅 crease in input current. The maximum differential input volt颅 age is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the nega颅 tive supply as this will cause large currents to flow which can result in a destroyed unit.
Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state.
These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common- mode voltage can exceed the positive supply by approxi颅
mately 100 my independent of supply voltage and over the full operating temperature range. The positive supply can
therefore be used as a reference on an input as, for exam颅
ple, in a supply current monitor and/or limiter.
Precautions should be taken to ensure that the power sup颅
pLy for the integrated circuit never becomes reversed in
Typical Circuit Connections
polarity or that the unit is not inadvertently installed back颅 wards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit.
Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.
All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage.
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in or颅 der to ensure stability. For example, resistors from the out颅 put to an input should be placed with the body close to the input to minimize 鈥減ickup鈥?and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capaci颅 tance from the input of the device (usually the inverting in颅 put) to ac ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.
0 Vos Adjustment
to to CO
4 to to
Co 2%
to 2_7
Driving Capacitive Loads LF157. A Large Power BW AmplifIer
- vwoAflv w 鈥?to to C鈥?
4 to to
LFIbt/W7
鈥?V05 is adiusted with a 25k potenti颅
鈥?The potentiometer wiper is con颅
nected to v4
. LF315a0
LF155/6 R=5k
LF157 R=1.25k
LF317 S 0 4e
TLJH/5548鈥?5
For distortion 1% and a 20 vp-p VOuT awing, power bandwidth is: 500 kHz.
to 鈥?For potentiometers with tempera颅
to ture coefficient of 100 ppm/鈥檆 or
IL less the additional drift with adjust
-I is Z 0.5 VJ鈥檆/mv of adjustment
鈥?Typical overall drift 5 jsvjc 卤 C0.5
V/鈥機/mV of adi.)
Due to a unique output stage design, these am颅
plifiers have the ability to drive large capacitive
loads and alill maintain stability. CMJO 0.01 gF.
Overshoot EI 20%
Settling time (t2) 5 s
Typical Applications
Settling Time Test Circuit
4U,II% 2
It鈥檇 r LF3II鈥?7 .1.
44II VOlT
III 0 鈥? Settling time is tested with the LFI 55)6 connected
3k es unity gain inverter end LF157 connected for
脌y = 鈥?
II. 0.1% 鈥? FET used to isolate the probe capacitance
v 鈥? Output= lGvstep
OICILLISCOPI 204411 o.nv 鈥? Ay 鈥?forLFl57
TIJH)5648-16
Large Signal inverter Output, VO1JT (from Settling Time Circuit)
LF355 13356 LF357
2 ga/DIV JaIDIV 1 ga/DIV
TL/H/5646鈥?7 TLIHI5S4O鈥?8 TL/H/5646鈥?9
Low Drift Adjustable Voltage Reference
鈥? a V1j-/.T= 卤O.002%PC
211413 I All resistors and potenliometers should be wire-wound
鈥? P1:drtftadjust
P1 鈥? P2: VOUT adjust
鈥? UseLFl55for
鈥?Low ID
OVOUT.1OV 鈥owdritt
鈥?Low supply current
III LF314 t-
113 lie
TLJH/5646-20
Typical Applications (Continued)
4 Fast Logarithmic Converter
C, 43 pF
鈥? Dynamic range: 100 MA EI I EI 1 mA (5 de颅
ades), vol = 1 V/decade
in -J 7 . Translentresponse:3psstorM1= idecade
01 O Wow -
LF 4 9 Lmma
鈥? Cl, C2, R2, R3: added dynamic compensation
V ad(ust the LF1 56 to rninlnte quiescent errot
4 鈥? Ry:TelLabstypeO8l + 0.3%/鈥機
10 鈥攍iv fil A p7
I鈥?TL/H/5646鈥?1
l.a. IVouTI = [1 +
鈥?mV1 [_鈥?._] = log V1 A2 = 15.7k, RT = 1k, O.3%PC (icr temperature compensation)
AT q
VREFRi AjIr
Precision Current Monitor
_I 40 I .
鈥? Vo=5A1/R2(V/mAoJl& Al, R2, R3: 0.1% resistors
10 3 LP3U snmu 鈥?LI. Ii +
Use LFl55Ior
鈥?Common-mode range to supply range
.1 鈥OWIB (0 鈥?Low V5
1.0 I Low Supply Current
TLIH/564e-31
ii. 8Bit D/A Converter with Symmetricai Offset Binary Operation
10 Vt. U,
4 liv Ii Ii ii iS iNi
U, , 1lS!1J171t1t1I!1l1鈥橧l,
CI) VifllIV
U 15CM LF3II F0
ii. T1f2 鈥?
CU 1鈥l
ill.. 鈥擨IV TL/H/5e4e鈥?2
4 鈥? Ri, R2 should be metched within 卤0.05%
in 鈥? Full-scale response time: 3M
U, E0 101 02 B3 04 05 BC B? BB Comments
r + 9.920 1 1 1 1 1 1 1 1 Positive FuIi-Scaie
-4-0.040 1 0 0 0 0 0 0 0 (+)Zero-Scaie
鈥?.040 0 1 1 1 1 1 1 1 (鈥?Zero-Scaie
鈥?.920 0 0 0 0 0 0 0 0 Negative FuIi-Scaie
Typical Applications (Continued) Wide BW Low Noise, Low Drift Amplifier
Isolating Large CapacItive Loads
A 鈥樎?5T
iiC Ii - I
鈥?20514
a-ti 鈥?7 鈥極UT
LFI5I U
1 鈥? Ilk
I. uF
CI) C,鈥?Cm
C鈥? Cm Cm
鈥?PowerBW:fMA =
鈥?Overshoot 6% TL/H/5646-22
鈥?t5 10 j*s
鈥?When driving large Cb the O鈥橨T slew rate determined by CL and
鈥?Parasitic input capacitance Cl (3 pF for LF1 55, LF1 56 and LF157 plus any additional layout capacitance) interacts with feedback elements and
creates undesirable high frequency pole. To compensate add C2 such that: R2C2 Rid.
1OUT(MPX)
= 0.04 V/s (with CL shown
Boosting the LF156 with a Current Amplifier
Low Drift Peak Detector
鈥? V.. S +104
+154 sat
鈥淲fl - 7
2 7 ci
C %%%41 - i
l.1a1 I
鈥?1::鈥?0IT
02 RIlE I
LF3B l
LF3IAII>
鈥?3 LIIIC
i 2.Il.1.
_L0111,
+ -.1_c,
TL/H/5646
鈥?By adding Di and R1, VD1 = 0 during hold mode. Leakage of 02 proved
by feedback path through Af.
-n Ca Cm
鈥?鈥榦ur(MAJQ150 mA (will drive RL 1000)
鈥Vour 0.15
T jj-j V/p.s (with CL shown)
鈥?No additional phase shift added by the currant amplifier
3 Decades VCO
III aF .154
鈥?Leakage of circuit is essentially lb (LF155, LF156) plus capacitor leakage
鈥?Diode 03 clamps Vojjr (Al) to VIN鈥擵D3 to improve speed and to limit reverse bias ot D2.
鈥?Maximum input frequency should be << 鈥?airRtCo2 where C02 is the shunt capacitance of 02.
Non-Inverting Unity Gain Operation for LF157
VgC C .5 ti
R1C (2w) (5MHz)
1551 Avt00) = 1
LFM5Vi颅
ueii H SI
f_3dBz5MHz
lea -liv
RAIn, i
鈥? 03
Inverting Unity Gain for LF157
- R1C (MH)
TL/H/5e46-24
VG(R8+R7)
(BVpR6R1)C OIV0I30V. 10 HzIfIlOkHz
Ri, R4 matched. LinearIty 0.1% over 2 decades.
+ Avt00) = 鈥?
1鈥? dO 5 MHz
TLJH/5646鈥?5
Typical Applications (Continued)
F- High impedance, Low Drift Instrumentation Amplifier
IL + 0 +
_1 R R3
I鈥?LF3II $ IS)
_.I .1W
鈥擣.鈥?鈥?4
F- Ri LIIA
1 8 .鈥?$y$ +
(0 鈥攍iv to
ASU LFISS
(0 -o + (
to C, IL
._J -liv
(0 R312R2
tO 鈥? VOUT i- Lii + 1] AVV- + 2V EI ViNcommon-mode EIV
IL 鈥? System Vos adjusted via A2 V05 adjust
TL/H15646鈥?6
U, U, C,
U, U, C, IL
U, U, r IL.
鈥? Trim R3 to boost up CMRR to 120 dB. instrumentation amplifier resistor array recommended for besl accuracy arid lowest &ift
Typical Applications (Continued)
Fast Sample and Hold
鈥? 鈥? SW?
PET SWITCHES 2
LFIIUI S
2 SWI AZ
鈥? j_,. LF355 aliT
+ 鈥極UT
鈥?Both amplifiers (Al, A2) have feedback loops individually closed with stable responses (overshoot negligible)
鈥?Acquisition time TA, estimated by: [2RQN. VIN, 0h 录 provided that:
I. sr j
VIN < 2lrSr RON Ch and TA> VIN Ch RON is of SW1
1OuT(MAX)
TtJH)5646鈥?3
If inequality not satisfied: TA
鈥?LF156 develops full Sr output capability for VIN 1V
鈥?Addition of SW2 introves accuracy by putting the voltage drop across SW1 inside the feedback loop
鈥?Overall accuracy of system determined by the accuracy of both amplifiers. At and A2
HIgh Accuracy Sample and Hold
I ._i鈥橠鈥濃€欌€?
SWITCHES H
2 1 LFII3I3 I H
SWt LF355
LF3II + 4
鈥?By closing the toop through A2, the VOuT accuracy will be determined uniquely by Al. No V adjust required for A2.
鈥?TA can be estimated by same conSiderationS as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
鈥?Overall system slower than fast sample and hold
鈥?RI, Crj additional compensation
鈥?Use LF156 for
鈥?Fast settling time
鈥?Low V05
TL/H/5646鈥?7
Typical Applications (Continued)
High 0 Band Pass Filter
LL 1111111
By adding positive feedback (R2)
to RI 6.1 pF
0 increases to 40
IL C2 in 鈥?W 1 BP 100 kHz
RI DJ6IpF 1 620101jfl
s11s2_
to LF3IT
鈥? . Clean layout recommended
1. + 4 LF351 fi 鈥esponsetoal Vp-ptone burst:
+ 4LtjJ
CD -isv
CD to CO
TL/Hf5646鈥?e
CD High 0 Notch Filter
鈥?R1=R=IOMO
to 2C=C1=300pF
it 鈥?Capacitors should be matched to obtain high 0
tnis 0 0v001 鈥?1NOTCH = 120 Hz, notch = 鈥?5 dB, 0 > A R 100
vwO S rS + 鈥seLFlssfor
I Low l
CO 鈥?Low supply current
to to C鈥?
4 to to C鈥?
to to C鈥?
to to Cs鈥?Ll
4 to to
拢 C rL/H/5646鈥?4

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2SA1227 datasheet

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2SA1 227/2SC2987,2SA1 227A/2SC2987A
PNPXE97JL-/flStfl&Jlfl-V D> F9鈥?X
PNP Silicon Epitaxial/NPN Silicon Triple Diffused Transistor
Audio Frequency Power Amplifier
hFbc鈥? Is! f0flLz5t
tijMli4R fTL鈥?<, EBTfA2Q)ttpfll: t 鈥? 1550W 55&IStLZ S
XShitOh7O W60 W (Singl鈥? PP, Rj8 Cl)51,1: lt鈥檌jk)hPjloo W鈥?20 W (Para PP, R18 Cl 2)i,
*S5***8 ABSOLUTE MAXIMUM RATINGS lTa鈥?5 tI
29 II 03 15 2SA1227 2SA3227A
29鈥?xW 140 160
29 鈥?2 9)9111:1 V1 140 160
VFRO 5.0
U U 2 9鈥?fta 1: 12
鈥?9[1E1fL 鈥樷€業PX Ill鈥? * 20
鈥?: Iii 51 Fr1, 020
P z 1鈥?_55150
*PWDIO ms, Duty cycic Xo
2SC2007 25C2087A ipf7
140 160 V
140 160 V
5s鈥?+150 t
tB44I卤 ELECTRICAL CHARACTERISTICS (Ta鈥?5 t)
ii l0 5 55 II鈥?2t鈥?9L.D鈥?3iif 鈥?try Vy 140 V 1 0
2 / 9 U 鈥?ft51ot Ittio Vy 3 V It 0
2001777, 2S012770 20C2987
MIN. TYP.
20C20070
MAX. Oilc1:
5050 pA
50 50 pA
WI1 1510501555 I1FEI 0V,I2A *
51551:15500鈥橲 V5V,I1 SA *
60 130 320
40 110 120
u 2 9015155鈥橝)t Vtpturt
5.0 A, ly 0.SA *
0.80.6 i.s 1.5 V
鈥?00)l1鈥橲Jt Vyt 115,0A,1 ISA *
Oil ic 鈥?)鈥? 05 00 05 V1 SV, I鈥? A
Ut鈥? 7 951W C Vpy-t0V,I0,f 1MHz
0鈥? /.2 ,0iL Pulse Test PWU350 y鈥檚, Duty Cycle 鈥?
h,-5, 1 5:60 120 Q: 100 200 p: 160 320
1.5 1.4 鈥?.0 2.0 V
60 50 MHz
280 100 pF